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SubjectRe: [patch] enabling APIC and NMI watchdog on UP systems
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> > ... and adds the enabling code of Keith Owens which
> > programs P6 performance counter 0 as an NMI. (i simplified the code alot -
> > there is no problem at all with getting NMIs from two sources, and it's
> > not necessary to make it configurable.)
>
> Is it really necessary to use one of the event counters ? this means those
> of us using event counters from modules can't use this oopser at
> the same time, which is a pity.

Indeed. What was wrong with the existing method, where you route an
external timer in AEOI mode through LVT0? Is it inefficient, or known
to fail on some boards, or something like that?

Another question relating to the setup of local APICs on current
-testX kernels: how are external interrupts routed through to the
processor? I thought that setup_local_APIC() used LVT0 to pick up
external interrupts, but setup_nmi_watchdog() reconfigures LVT0 into
NMI mode!

On my SMP box, running test6, the following line:
printk("CPU#%d: %08x/%08x\n", smp_processor_id(),
apic_read(APIC_LVT0), apic_read(APIC_LVT1));

yields the result:
CPU#0: 00000400/00000400
CPU#1: 00000400/00010400

That is, all the LINT[0:1] pins on all processors are configured into
NMI mode. That given, I don't see how external interrupts work
(although obviously they must do :-)

I'm really curious as to how this magic works...

-- Keir Fraser
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