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SubjectRe: New topic (PowerPC Linux PCI HELL)

On Fri, 22 Sep 2000, Jamie Lokier wrote:

> Michel Lanners wrote:
> > >> static inline int pci_enable_device(struct pci_device *dev)
> > >> {
> > >> return pci_enable_device_features(USE_IO|USE_MM);
> > >> }
> > (snip)
> > > And what about other features ?
> > > I mean:
> > > - Bus Master
> > > - Memory Write and Invalidate
> > > - Parity Error response
> >
> > This should probably be handled in arch-dependant code. So make a
> > pci_enable_device() per arch. The point beeing that only this code has a
> > chance to know some of the details of the PCI implementation on this
> > platform/arch. Bus master and MemWI don't hurt, but I guess enabling
> > parity can halt the bus. So you want to be careful...
> Take a look at the drivers/net/acenic.c driver. It enables/disables
> Memory Write and Invalidate one way or another, but the decision is not
> arch-specific. It gets worse: it writes cache line size to PCI_COMMAND
> as well.

Why should it not do so, given that no hardware quirks is supplied ?

The fact that you aren't told about something should not make you assume
the worse case, by default. Such behaviour is called paranoia. And,
speaking about PCI, result is that users pay for features the kernel
decide in user's back not to use, even when they are functionning just

About PCI parity error checking and reporting, this feature is required
for most PCI controller classes. If it is confusing the machine, then
hardware should get garbagged and user should get reimbursed of the
hardware and time wasted.

About the PCI cache line size, there is no valuable reason for the POST
code not to set it. Obviously, MWI requires the right value of the cache
line to be configured. A POST code that does not set the cache line size
to the proper value in order to tell about not using MWI looks like a
definite piece of crap to me. PCI devices may use the configured cache
line size in order to make decision about using MRL and MRM as you know,
and bridges and devices that implement prefetchable memory can gain
advantage of such transactions.

Note that for MRL and MRM, assuming a wrong value of the cache line size
will not break anything, and a not too wrong value (twice or half the
right value) can be adequate.


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