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SubjectVIA IDE v3.0 preview
Hi!

For those who are interested in testing my VIA IDE code, here is another
release that configures the thing even better. IDE timing is black
magic. ;) It's a drop-in replacement for the 2.1 driver.

I'm interested in failure/success reports.

Thanks.

--
Vojtech Pavlik
SuSE Labs
#ifndef _IDE_TIMING_H
#define _IDE_TIMING_H

/*
* $Id: ide-timing.h,v 1.0 2000/09/17 00:34:56 vojtech Exp $
*
* Copyright (c) 1999-2000 Vojtech Pavlik
*
* Sponsored by SuSE
*/

/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
* Should you need to contact me, the author, you can do so either by
* e-mail - mail your message to <vojtech@suse.cz>, or by paper mail:
* Vojtech Pavlik, Ucitelska 1576, Prague 8, 182 00 Czech Republic
*/

#include <linux/hdreg.h>

#ifndef XFER_PIO_5
#define XFER_PIO_5 0x0d
#endif

struct ide_timing {
short mode;
short setup; /* t1 */
short act8b; /* t2 for 8-bit io */
short rec8b; /* t2i for 8-bit io */
short cyc8b; /* t0 for 8-bit io */
short active; /* t2 or tD */
short recover; /* t2i or tK */
short cycle; /* t0 */
short udma; /* t2CYCTYP/2 */
};

/*
* PIO 0-5, MWDMA 0-2 and UDMA 0-5 timings (in nanoseconds).
* These were taken from ATA/ATAPI-6 standard, rev 0a, except
* for PIO 5, which is a nonstandard extension.
*/

static struct ide_timing ide_timing[] = {

{ XFER_UDMA_5, 0, 0, 0, 0, 0, 0, 0, 20 },
{ XFER_UDMA_4, 0, 0, 0, 0, 0, 0, 0, 30 },
{ XFER_UDMA_3, 0, 0, 0, 0, 0, 0, 0, 45 },

{ XFER_UDMA_2, 0, 0, 0, 0, 0, 0, 0, 60 },
{ XFER_UDMA_1, 0, 0, 0, 0, 0, 0, 0, 80 },
{ XFER_UDMA_0, 0, 0, 0, 0, 0, 0, 0, 120 },

{ XFER_MW_DMA_2, 25, 0, 0, 0, 70, 25, 120, 0 },
{ XFER_MW_DMA_1, 45, 0, 0, 0, 80, 50, 150, 0 },
{ XFER_MW_DMA_0, 60, 0, 0, 0, 215, 215, 480, 0 },

{ XFER_SW_DMA_2, 60, 0, 0, 0, 120, 120, 240, 0 },
{ XFER_SW_DMA_1, 90, 0, 0, 0, 240, 240, 480, 0 },
{ XFER_SW_DMA_0, 120, 0, 0, 0, 480, 480, 960, 0 },

{ XFER_PIO_5, 20, 50, 30, 100, 50, 30, 100, 0 },
{ XFER_PIO_4, 25, 70, 25, 120, 70, 25, 120, 0 },
{ XFER_PIO_3, 30, 80, 70, 180, 80, 70, 180, 0 },

{ XFER_PIO_2, 30, 290, 40, 330, 100, 90, 240, 0 },
{ XFER_PIO_1, 50, 290, 93, 383, 125, 100, 383, 0 },
{ XFER_PIO_0, 70, 290, 240, 600, 165, 150, 600, 0 },

{ XFER_PIO_SLOW, 120, 290, 240, 960, 290, 240, 960, 0 },

{ -1 }
};

#define IDE_TIMING_SETUP 0x01
#define IDE_TIMING_ACT8B 0x02
#define IDE_TIMING_REC8B 0x04
#define IDE_TIMING_CYC8B 0x08
#define IDE_TIMING_8BIT 0x0e
#define IDE_TIMING_ACTIVE 0x10
#define IDE_TIMING_RECOVER 0x20
#define IDE_TIMING_CYCLE 0x40
#define IDE_TIMING_UDMA 0x80
#define IDE_TIMING_ALL 0xff

#define MIN(a,b) ((a)<(b)?(a):(b))
#define MAX(a,b) ((a)>(b)?(a):(b))
#define FIT(v,min,max) MAX(MIN(v,max),min)
#define ENOUGH(v,unit) (((v)-1)/(unit)+1)
#define EZ(v,unit) ((v)?ENOUGH(v,unit):0)

#define XFER_MODE 0xf0
#define XFER_UDMA_100 0x44
#define XFER_UDMA_66 0x42
#define XFER_UDMA 0x40
#define XFER_MWDMA 0x20
#define XFER_SWDMA 0x10
#define XFER_EPIO 0x01
#define XFER_PIO 0x00

static short ide_find_best_mode(ide_drive_t *drive, int map)
{
struct hd_driveid *id = drive->id;
short best = 0;

if (!id)
return XFER_PIO_SLOW;

if ((map & XFER_UDMA) && (id->field_valid & 4)) { /* Want UDMA and UDMA bitmap valid */

if (map & XFER_UDMA_100)
if ((best = (id->dma_ultra & 0x0020) ? XFER_UDMA_5 : 0)) return best;

if (map & XFER_UDMA_66)
if ((best = (id->dma_ultra & 0x0010) ? XFER_UDMA_4 :
(id->dma_ultra & 0x0008) ? XFER_UDMA_3 : 0)) return best;

if ((best = (id->dma_ultra & 0x0004) ? XFER_UDMA_2 :
(id->dma_ultra & 0x0002) ? XFER_UDMA_1 :
(id->dma_ultra & 0x0001) ? XFER_UDMA_0 : 0)) return best;
}

if ((map & XFER_MWDMA) && (id->field_valid & 2)) { /* Want MWDMA and drive has EIDE fields */

if ((best = (id->dma_mword & 0x0004) ? XFER_MW_DMA_2 :
(id->dma_mword & 0x0002) ? XFER_MW_DMA_1 :
(id->dma_mword & 0x0001) ? XFER_MW_DMA_0 : 0)) return best;
}

if (map & XFER_SWDMA) { /* Want SWDMA */

if (id->field_valid & 2) { /* EIDE SWDMA */

if ((best = (id->dma_1word & 0x0004) ? XFER_SW_DMA_2 :
(id->dma_1word & 0x0002) ? XFER_SW_DMA_1 :
(id->dma_1word & 0x0001) ? XFER_SW_DMA_0 : 0)) return best;
}

if (id->capability & 1) { /* Pre-EIDE style SWDMA */

if ((best = (id->tDMA == 2) ? XFER_SW_DMA_2 :
(id->tDMA == 1) ? XFER_SW_DMA_1 :
(id->tDMA == 0) ? XFER_SW_DMA_0 : 0)) return best;
}
}


if ((map & XFER_EPIO) && (id->field_valid & 2)) { /* EIDE PIO modes */

if ((best = (drive->id->eide_pio_modes & 4) ? XFER_PIO_5 :
(drive->id->eide_pio_modes & 2) ? XFER_PIO_4 :
(drive->id->eide_pio_modes & 1) ? XFER_PIO_3 : 0)) return best;
}

return (drive->id->tPIO == 2) ? XFER_PIO_2 :
(drive->id->tPIO == 1) ? XFER_PIO_1 :
(drive->id->tPIO == 0) ? XFER_PIO_0 : XFER_PIO_SLOW;
}

static void ide_timing_quantize(struct ide_timing *t, struct ide_timing *q, int T, int UT)
{
q->setup = EZ(t->setup, T);
q->act8b = EZ(t->act8b, T);
q->rec8b = EZ(t->rec8b, T);
q->cyc8b = EZ(t->cyc8b, T);
q->active = EZ(t->active, T);
q->recover = EZ(t->recover, T);
q->cycle = EZ(t->cycle, T);
q->udma = EZ(t->udma, UT);
}

static void ide_timing_merge(struct ide_timing *a, struct ide_timing *b, struct ide_timing *m, unsigned int what)
{
if (what & IDE_TIMING_SETUP ) m->setup = MAX(a->setup, b->setup);
if (what & IDE_TIMING_ACT8B ) m->act8b = MAX(a->act8b, b->act8b);
if (what & IDE_TIMING_REC8B ) m->rec8b = MAX(a->rec8b, b->rec8b);
if (what & IDE_TIMING_CYC8B ) m->cyc8b = MAX(a->cyc8b, b->cyc8b);
if (what & IDE_TIMING_ACTIVE ) m->active = MAX(a->active, b->active);
if (what & IDE_TIMING_RECOVER) m->recover = MAX(a->recover, b->recover);
if (what & IDE_TIMING_CYCLE ) m->cycle = MAX(a->cycle, b->cycle);
if (what & IDE_TIMING_UDMA ) m->udma = MAX(a->udma, b->udma);
}

static struct ide_timing* ide_timing_find_mode(short speed)
{
struct ide_timing *t;

for (t = ide_timing; t->mode != speed; t++)
if (t->mode < 0)
return NULL;
return t;
}

static int ide_timing_compute(ide_drive_t *drive, short speed, struct ide_timing *t, int T, int UT)
{
struct hd_driveid *id = drive->id;
struct ide_timing *s, p;

/*
* Find the mode and compute base timing.
*/

if (!(s = ide_timing_find_mode(speed)))
return -EINVAL;

ide_timing_quantize(s, t, T, UT);

/*
* If the drive is an EIDE drive, it can tell us it needs extended
* PIO/MWDMA cycle timing. For MWDMA it also specifies recommended
* cycle timing.
*/

if (id && id->field_valid & 2) { /* EIDE drive */

switch (speed & XFER_MODE) {

case XFER_PIO:

if (speed <= XFER_PIO_2) {
t->cyc8b = MAX(t->cyc8b, ENOUGH(id->eide_pio, T));
t->cycle = MAX(t->cycle, ENOUGH(id->eide_pio, T));
break;
}

t->cyc8b = MAX(t->cyc8b, ENOUGH(id->eide_pio_iordy, T));
t->cycle = MAX(t->cycle, ENOUGH(id->eide_pio_iordy, T));
break;

case XFER_MWDMA:

t->cycle = MAX(t->cycle, id->eide_dma_time / T);
t->cycle = MAX(t->cycle, ENOUGH(id->eide_dma_min, T));
break;
}
}

/*
* Even in DMA/UDMA modes we still use PIO access for IDENTIFY, S.M.A.R.T
* and some other commands. We have to ensure that the DMA cycle timing is
* slower/equal than the fastest PIO timing.
*/

if ((speed & XFER_MODE) != XFER_PIO) {
ide_timing_compute(drive, ide_find_best_mode(drive, XFER_PIO | XFER_EPIO), &p, T, UT);
ide_timing_merge(&p, t, t, IDE_TIMING_ALL);
}

/*
* Lenghten active & recovery time so that cycle time is correct.
*/

if (t->act8b + t->rec8b < t->cyc8b) {
t->act8b += (t->cyc8b - (t->act8b + t->rec8b)) / 2;
t->rec8b = t->cyc8b - t->act8b;
}

if (t->active + t->recover < t->cycle) {
t->active += (t->cycle - (t->active + t->recover)) / 2;
t->recover = t->cycle - t->active;
}

return 0;
}

#endif
/*
* $Id: via82cxxx.c,v 3.0 2000/09/17 12:52:60 vojtech Exp $
*
* Copyright (c) 2000 Vojtech Pavlik
*
* Based on the work of:
* Michel Aubry
* Jeff Garzik
* Andre Hedrick
*
* Sponsored by SuSE
*/

/*
* VIA vt82c586 IDE driver for Linux. Supports
*
* vt82c586, vt82c586a, vt82c586b, vt82c596a, vt82c596b, vt82c686a, vt8231
*
* southbridges, which can be found in
*
* VIA Apollo VP, VPX, VPX/97, VP2, VP2/97, VP3, MVP3, MVP4, Pro, Pro Plus,
* Pro 133, Pro 133A, ProMedia 601, ProSavage 605, ProSavage PM133, KX133, KT133
* PC-Chips VXPro, VXPro+, TXPro-III, TXPro-AGP, ViaGra, BXToo, BXTel
* AMD 640, 640 AGP, 750 IronGate
* ETEQ 6618, 6628, 6638
* Micron Samurai
*
* chipsets. Supports
*
* PIO 0-5, MWDMA 0-2, SWDMA 0-2 and UDMA 0-5
*
* (includes UDMA33, 66 and 100) modes. UDMA100 isn't possible
* on any of the supported chipsets yet. UDMA66 and higher modes are
* autodetected only in case the BIOS has enabled them. To force UDMA66,
* use 'ide0=ata66' or 'ide1=ata66' on the kernel command line.
*/

/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
* Should you need to contact me, the author, you can do so either by
* e-mail - mail your message to <vojtech@suse.cz>, or by paper mail:
* Vojtech Pavlik, Ucitelska 1576, Prague 8, 182 00 Czech Republic
*/

#include <linux/config.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/timer.h>
#include <linux/mm.h>
#include <linux/ioport.h>
#include <linux/interrupt.h>
#include <linux/blkdev.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/ide.h>
#include <asm/io.h>

#include "ide-timing.h"

#define VIA_BM_BASE 0x20
#define VIA_IDE_ENABLE 0x40
#define VIA_IDE_CONFIG 0x41
#define VIA_FIFO_CONFIG 0x43
#define VIA_MISC_1 0x44
#define VIA_MISC_2 0x45
#define VIA_MISC_3 0x46
#define VIA_DRIVE_TIMING 0x48
#define VIA_8BIT_TIMING 0x4e
#define VIA_ADDRESS_SETUP 0x4c
#define VIA_UDMA_TIMING 0x50
#define VIA_PRI_SECTOR_SIZE 0x60
#define VIA_SEC_SECTOR_SIZE 0x68

#define VIA_UDMA_NONE 0
#define VIA_UDMA_33 1
#define VIA_UDMA_66 2
#define VIA_UDMA_100 3

/*
* VIA SouthBridge chips.
*/

static struct via_isa_bridge {
char *name;
unsigned short id;
unsigned char rev;
unsigned char udma;
} via_isa_bridges[] = {
{ "vt8231", PCI_DEVICE_ID_VIA_8231, 0x00, VIA_UDMA_66 },
{ "vt82c686a", PCI_DEVICE_ID_VIA_82C686, 0x10, VIA_UDMA_66 },
{ "vt82c686", PCI_DEVICE_ID_VIA_82C686, 0x00, VIA_UDMA_66 },
{ "vt82c596b", PCI_DEVICE_ID_VIA_82C596, 0x10, VIA_UDMA_66 },
{ "vt82c596a", PCI_DEVICE_ID_VIA_82C596, 0x00, VIA_UDMA_33 },
{ "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x30, VIA_UDMA_33 },
{ "vt82c586a", PCI_DEVICE_ID_VIA_82C586_0, 0x20, VIA_UDMA_33 },
{ "vt82c586", PCI_DEVICE_ID_VIA_82C586_0, 0x00, VIA_UDMA_NONE },
{ NULL }
};

static struct via_isa_bridge *via_config;
static unsigned char via_enabled;
static unsigned int via_ata66;

/*
* VIA /proc entry.
*/

#ifdef CONFIG_PROC_FS

#include <linux/stat.h>
#include <linux/proc_fs.h>

int via_proc = 0;
static struct pci_dev *bmide_dev, *isa_dev;
extern int (*via_display_info)(char *, char **, off_t, int); /* ide-proc.c */

static char *via_fifo[] = { " 1 ", "3/4", "1/2", "1/4" };
static char *via_control3[] = { "No limit", "64", "128", "192" };

#define via_print(format, arg...) p += sprintf(p, format "\n" , ## arg)
#define via_print_drive(name, format, arg...)\
p += sprintf(p, name); for (i = 0; i < 4; i++) p += sprintf(p, format, ## arg); p += sprintf(p, "\n");

static int via_get_info(char *buffer, char **addr, off_t offset, int count)
{
short pci_clock, speed[4], cycle[4], setup[4], active[4],
recover[4], umul[4], uen[4], udma[4], active8b[4], recover8b[4];
struct pci_dev *dev = bmide_dev;
unsigned int v, u, i, base;
unsigned short c, w, size0, size1;
unsigned char t;
char *p = buffer;

via_print("----------VIA BusMastering IDE Configuration----------------");

via_print("Driver Version: 3.0");

pci_read_config_byte(isa_dev, PCI_REVISION_ID, &t);
via_print("South Bridge: VIA %s rev %#x", via_config->name, t);

pci_read_config_byte(dev, PCI_REVISION_ID, &t);
via_print("IDE type: Apollo VP rev %#x", t);

pci_read_config_word(dev, PCI_COMMAND, &c);
via_print("Command register: %#x", c);

pci_read_config_byte(dev, PCI_LATENCY_TIMER, &t);
via_print("Latency timer: %d", t);

pci_clock = system_bus_clock();
via_print("PCI clock: %dMHz", pci_clock);

pci_read_config_byte(dev, VIA_MISC_1, &t);
via_print("Master Read Cycle IRDY: %dws", (t & 64) >> 6);
via_print("Master Write Cycle IRDY: %dws", (t & 32) >> 5);
via_print("FIFO Output Data 1/2 Clock Advance: %s", (t & 16) ? "on" : "off" );
via_print("BM IDE Status Register Read Retry: %s", (t & 8) ? "on" : "off" );

pci_read_config_byte(dev, VIA_MISC_2, &t);
sprintf(p, "Interrupt Steering Swap: %s", (t & 64) ? "on" : "off");

pci_read_config_byte(dev, VIA_MISC_3, &t);
via_print("Max DRDY Pulse Width: %s%s", via_control3[(t & 0x03)], (t & 0x03) ? "PCI clocks" : "");

via_print("-----------------------Primary IDE-------Secondary IDE------");
via_print("Read DMA FIFO flush: %10s%20s", (t & 0x80) ? "on" : "off", (t & 0x40) ? "on" : "off" );
via_print("End Sect. FIFO flush: %10s%20s", (t & 0x20) ? "on" : "off", (t & 0x10) ? "on" : "off" );

pci_read_config_byte(dev, VIA_IDE_CONFIG, &t);
via_print("Prefetch Buffer: %10s%20s", (t & 0x80) ? "on" : "off", (t & 0x20) ? "on" : "off" );
via_print("Post Write Buffer: %10s%20s", (t & 0x40) ? "on" : "off", (t & 0x10) ? "on" : "off" );

pci_read_config_byte(dev, VIA_FIFO_CONFIG, &t);
via_print("FIFO Size: %10d%20d", 16 - (((t >> 5) & 1) + ((t >> 6) & 1)) * 8,
(((t >> 5) & 1) + ((t >> 6) & 1)) * 8);
via_print("FIFO Threshold: %10s%20s", via_fifo[(t >> 2) & 3], via_fifo[t & 3]);

pci_read_config_word(dev, VIA_PRI_SECTOR_SIZE, &size0);
pci_read_config_word(dev, VIA_SEC_SECTOR_SIZE, &size1);
via_print("Bytes Per Sector: %10d%20d", size0 & 0xfff, size1 & 0xfff);

pci_read_config_dword(dev, VIA_BM_BASE, &base);
base = (base & 0xfff0) ;

c = inb((unsigned short)base + 0x02) | (inb((unsigned short)base + 0x0a) << 8);

via_print("Both channels togth: %10s%20s", (c & 0x80) ? "no" : "yes", (c & 0x8000) ? "no" : "yes" );

via_print("-------------------drive0----drive1----drive2----drive3-----");

pci_read_config_byte(dev, VIA_ADDRESS_SETUP, &t);
pci_read_config_dword(dev, VIA_DRIVE_TIMING, &v);
pci_read_config_word(dev, VIA_8BIT_TIMING, &w);
pci_read_config_dword(dev, VIA_UDMA_TIMING, &u);

for (i = 0; i < 4; i++) {
setup[i] = ((t >> ((3 - i) << 1)) & 0x3) + 1;
recover8b[i] = ((w >> ((1 - (i >> 1)) << 3)) & 0xf) + 1;
active8b[i] = ((w >> (((1 - (i >> 1)) << 3) + 4)) & 0xf) + 1;
active[i] = ((v >> (((3 - i) << 3) + 4)) & 0xf) + 1;
recover[i] = ((v >> ((3 - i) << 3)) & 0xf) + 1;

udma[i] = ((u >> ((3 - i) << 3)) & 0x7) + 2;
umul[i] = ((u >> (((3 - i) & 2) << 3)) & 0x8) ? 2 : 1;
uen[i] = ((u >> ((3 - i) << 3)) & 0x20) ? 1 : 0;

speed[i] = uen[i] ? 20 * pci_clock * umul[i] / udma[i] :
20 * pci_clock / (active[i] + recover[i]);
cycle[i] = uen[i] ? 1000 / (pci_clock * umul[i]) * udma[i] :
1000 / pci_clock * (active[i] + recover[i]);
}

via_print_drive("Transfer Mode: ", "%10s",
uen[i] ? "UDMA" : (c & ((i & 1) ? 0x40 : 0x20) << ((i & 2) << 2) ? "DMA" : "PIO"));

via_print_drive("Address Setup: ", "%8dns", (1000 / pci_clock) * setup[i]);
via_print_drive("Cmd Active: ", "%8dns", (1000 / pci_clock) * active8b[i]);
via_print_drive("Cmd Recovery: ", "%8dns", (1000 / pci_clock) * recover8b[i]);
via_print_drive("Data Active: ", "%8dns", (1000 / pci_clock) * active[i]);
via_print_drive("Data Recovery: ", "%8dns", (1000 / pci_clock) * recover[i]);
via_print_drive("Cycle Time: ", "%8dns", cycle[i]);
via_print_drive("Transfer Rate: ", "%4d.%dMB/s", speed[i] / 10, speed[i] % 10);

return p - buffer; /* hoping it is less than 4K... */
}

#endif
#ifdef DEBUG
#define via_write_config_byte(dev,number,value) do {\
printk(KERN_DEBUG "VP_IDE: Setting register %#x to %#x\n", number, value);\
pci_write_config_byte(dev,number,value); } while (0)
#else
#define via_write_config_byte pci_write_config_byte
#endif

/*
* via_set_speed() writes timing values to the chipset registers
*/

static void via_set_speed(struct pci_dev *dev, unsigned char dn, struct ide_timing *timing)
{
unsigned char t;

pci_read_config_byte(dev, VIA_ADDRESS_SETUP, &t);
t = (t & ~(3 << ((3 - dn) << 1))) | (FIT(timing->setup - 1, 0, 3) << ((3 - dn) << 1));
via_write_config_byte(dev, VIA_ADDRESS_SETUP, t);

via_write_config_byte(dev, VIA_8BIT_TIMING + (1 - (dn >> 1)),
(FIT(timing->act8b - 1, 0, 0xf) << 4) | FIT(timing->rec8b - 1, 0, 0xf));

via_write_config_byte(dev, VIA_DRIVE_TIMING + (3 - dn),
(FIT(timing->active - 1, 0, 0xf) << 4) | FIT(timing->recover - 1, 0, 0xf));

if (timing->udma) {
t = 0xe8;
switch(via_config->udma) {
case VIA_UDMA_33: t |= FIT(timing->udma - 2, 0, 3); break;
case VIA_UDMA_66: t |= FIT(timing->udma - 2, 0, 7); break;
}
} else t = 0x0b;

via_write_config_byte(dev, VIA_UDMA_TIMING + (3 - dn), t);
}

/*
* via_set_drive() computes timing values configures the drive and
* the chipset to a desired transfer mode. It also can be called
* by upper layers.
*/

static int via_set_drive(ide_drive_t *drive, unsigned char speed)
{
ide_drive_t *peer = HWIF(drive)->drives + (~drive->dn & 1);
struct ide_timing t, p;
int err, T, UT;

T = 1000 / system_bus_clock();
UT = T / via_config->udma;

ide_timing_compute(drive, speed, &t, T, UT);

if (peer->present) {
ide_timing_compute(peer, peer->current_speed, &p, T, UT);
ide_timing_merge(&p, &t, &t, IDE_TIMING_8BIT);
}

via_set_speed(HWIF(drive)->pci_dev, drive->dn, &t);

if (!drive->init_speed)
drive->init_speed = speed;

if (speed != XFER_PIO_SLOW && speed != drive->current_speed) {
if ((err = ide_config_drive_speed(drive, speed)))
return err;
drive->current_speed = speed;
}

return 0;
}

/*
* via82cxxx_tune_drive() is a callback from upper layers for
* PIO-only tuning.
*/

static void via82cxxx_tune_drive(ide_drive_t *drive, unsigned char pio)
{

if (!((via_enabled >> HWIF(drive)->channel) & 1))
return;

if (pio == 255) {
via_set_drive(drive, ide_find_best_mode(drive, XFER_PIO | XFER_EPIO));
return;
}

via_set_drive(drive, XFER_PIO_0 + MIN(pio, 5));
}

#ifdef CONFIG_BLK_DEV_IDEDMA

/*
* via82cxxx_dmaproc() is a callback from upper layers that can do
* a lot, but we use ti for DMA/PIO tuning only, delegating everything
* else to the default ide_dmaproc().
*/

int via82cxxx_dmaproc(ide_dma_action_t func, ide_drive_t *drive)
{

if (func == ide_dma_check) {

short ata66 = eighty_ninty_three(drive);
short ata100 = 0;

short speed = ide_find_best_mode(drive,
XFER_PIO | XFER_EPIO | XFER_SWDMA | XFER_MWDMA |
(via_config->udma > VIA_UDMA_NONE ? XFER_UDMA : 0) |
(ata66 && via_config->udma > VIA_UDMA_66 ? XFER_UDMA_66 : 0) |
(ata100 && via_config->udma > VIA_UDMA_100 ? XFER_UDMA_100 : 0));

via_set_drive(drive, speed);

func = ((speed & XFER_MODE) != XFER_PIO) ? ide_dma_on : ide_dma_off_quietly;

}

return ide_dmaproc(func, drive);
}

#endif /* CONFIG_BLK_DEV_IDEDMA */

/*
* The initialization callback. Here we determine the IDE chip type
* and initialize its drive independent registers.
*/

unsigned int __init pci_init_via82cxxx(struct pci_dev *dev, const char *name)
{
struct pci_dev *isa = NULL;
unsigned char f, t, m;
unsigned int u;
int i;

/*
* Find ISA bridge to see how good the IDE is.
*/

for (via_config = via_isa_bridges; via_config->id; via_config++)
if ((isa = pci_find_device(PCI_VENDOR_ID_VIA, via_config->id, NULL))) {
pci_read_config_byte(isa, PCI_REVISION_ID, &t);
if (t >= via_config->rev)
break;
}

if (!via_config->id) {
printk(KERN_WARNING "VP_IDE: Unknown VIA SouthBridge, contact Vojtech Pavlik <vojtech@suse.cz>\n");
return -ENODEV;
}

/*
* Check UDMA66 mode set by BIOS & enable 66 MHz timing.
*/

pci_read_config_dword(dev, VIA_UDMA_TIMING, &u);
pci_write_config_dword(dev, VIA_UDMA_TIMING, u | 0x80008);

for (i = 24; i >= 0; i -= 8)
if (((u >> (i & 16)) & 8) && (((u >> i) & 7) < 2)) /* 2x PCI clock && less than 3T/cycle */
via_ata66 |= (1 << (1 - (i >> 4)));

#ifdef DEBUG
printk(KERN_DEBUG "VP_IDE: BIOS enabled ATA66: primary: %s, secondary: %s\n",
via_ata66 & 1 ? "yes" : "no", via_ata66 & 2 ? "yes" : "no");
#endif

/*
* Set up FIFO, flush, prefetch and post-writes.
*/

pci_read_config_dword(dev, VIA_IDE_ENABLE, &u);
pci_read_config_byte(dev, VIA_FIFO_CONFIG, &f);
pci_read_config_byte(dev, VIA_IDE_CONFIG, &t);
pci_read_config_byte(dev, VIA_MISC_3, &m);

f &= 0x90; t &= 0x0f; m &= 0x0f;

switch (u & 3) {
case 2: via_enabled = 1; f |= 0x06; t |= 0xc0; m |= 0xa0; break; /* primary only, 3/4 */
case 1: via_enabled = 2; f |= 0x69; t |= 0x30; m |= 0x50; break; /* secondary only, 3/4 */
case 3: via_enabled = 3;
default: f |= 0x2a; t |= 0xf0; m |= 0xf0; break; /* fifo evenly distributed */
}

via_write_config_byte(dev, VIA_FIFO_CONFIG, f);
via_write_config_byte(dev, VIA_IDE_CONFIG, t);
via_write_config_byte(dev, VIA_MISC_3, m);

/*
* Print the boot message.
*/

printk(KERN_INFO "VP_IDE: VIA %s IDE %s controller on pci%d:%d.%d\n",
via_config->name,
via_config->udma >= VIA_UDMA_66 ? "UDMA66" :
via_config->udma >= VIA_UDMA_33 ? "UDMA33" : "MWDMA16",
dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
/*
* Register /proc/ide/via entry
*/

#ifdef CONFIG_PROC_FS
if (!via_proc) {
via_proc = 1;
bmide_dev = dev;
isa_dev = isa;
via_display_info = &via_get_info;
}
#endif

return 0;
}

/*
* Since we don't have a way to detect the 80-wire ribbon cable
* we rely on the BIOS detection. We also check the IDENTIFY byte
* 93 to check the drive's point of view. I think we could return
* '1' here
*/

unsigned int __init ata66_via82cxxx(ide_hwif_t *hwif)
{
return ((via_enabled && via_ata66) >> hwif->channel) & 1;
}

void __init ide_init_via82cxxx(ide_hwif_t *hwif)
{
hwif->tuneproc = &via82cxxx_tune_drive;
hwif->speedproc = &via_set_drive;
hwif->drives[0].autotune = 1;
hwif->drives[1].autotune = 1;

/* Fix for broken ide-probe.c */
hwif->drives[0].dn = hwif->channel * 2 + 0;
hwif->drives[1].dn = hwif->channel * 2 + 1;

hwif->autodma = 0;

#ifdef CONFIG_BLK_DEV_IDEDMA
if (hwif->dma_base) {
hwif->dmaproc = &via82cxxx_dmaproc;
hwif->autodma = 1;
}
#endif /* CONFIG_BLK_DEV_IDEDMA */
}

/*
* We allow the BM-DMA driver only work on enabled interfaces.
*/

void ide_dmacapable_via82cxxx(ide_hwif_t *hwif, unsigned long dmabase)
{
if ((via_enabled >> hwif->channel) & 1)
ide_setup_dma(hwif, dmabase, 8);
}
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