Messages in this thread |  | | Date | Sat, 26 Aug 2000 23:19:43 -0700 (PDT) | From | Andre Hedrick <> | Subject | Re: UDMA trouble in VT82C586 IDE |
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Hi Cesar,
All Vojtech has to do is accept responsiblity for the chipset code. I mean all flavors of the bastardization of the design. This includes the ones that you can change the chipset reporting type if you know the dirty-secrets. The problem is that some mainboard manufacturers alter the PCI ID codes to fake compatablity.
Now if your board is one of these boards, then I would expect it to not work.
On Sat, 26 Aug 2000, Cesar Eduardo Barros wrote:
> > It works great now. I got a month-old full rewrite of via82cxxx.c from > Vojtech Pavlik in the lkml archives and compiled it. > > Linus: I think it should be included. The old driver is messy, hairy, and fails > to work here. The new one is clean, neat, and works fine. If you lost the
Just because you have a newer wierder combination does not mean the old and lousy is junk.
Again, if Vojtech will put it on the line that compatablity/support is better go for it. In the past Vojtech was not ready to jump on this and run. I have one, and only one, completely corrupted drive, beyond recovery by any means, because of one incomplete thought in the design.
I will not accept this happenning again.
> message I can send you the copy of the driver I got here. > > Uniform Multi-Platform E-IDE driver Revision: 6.31 > ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx > VP_IDE: IDE controller on PCI bus 00 dev 39 > VP_IDE: chipset revision 6 > VP_IDE: not 100% native mode: will probe irqs later > VP_IDE: VIA vt82c686a IDE UDMA66 controller on pci0:7.1 > ide0: BM-DMA at 0xffa0-0xffa7, BIOS settings: hda:DMA, hdb:pio > ide1: BM-DMA at 0xffa8-0xffaf, BIOS settings: hdc:pio, hdd:pio > hda: ST320423A, ATA DISK drive > ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx > hdc: CR-2802TE, ATAPI CDROM drive > ide0 at 0x1f0-0x1f7,0x3f6 on irq 14 > ide1 at 0x170-0x177,0x376 on irq 15 > hda: 40011300 sectors (20486 MB) w/512KiB Cache, CHS=2490/255/63, UDMA(66) > Partition check: > hda: hda1 > > /proc/ide$ cat via > ----------VIA BusMastering IDE Configuration----------------- > Command register: 0x7 > Latency timer: 32 > Master Read Cycle IRDY: 0ws > Master Write Cycle IRDY: 0ws > FIFO Output Data 1/2 Clock Advance: off > BM IDE Status Register Read Retry: on > Max DRDY Pulse Width: No limit > -----------------------Primary IDE-------Secondary IDE------- > Read DMA FIFO flush: on on > End Sect. FIFO flush: on on > Prefetch Buffer: on on > Post Write Buffer: on on > FIFO size: 8 8 > Threshold Prim.: 1/2 1/2 > Bytes Per Sector: 512 512 > Both channels togth: yes yes > -------------------drive0----drive1----drive2----drive3----- > BMDMA enabled: yes no no no > Transfer Mode: UDMA DMA/PIO DMA/PIO DMA/PIO > Cycle (T): 15ns 30ns 30ns 30ns > Address Setup: --- 3T 2T 4T > Active Pulse: --- 11T 4T 11T > Recovery Time: --- 9T 2T 9T > Cycle Time: 2T 23T 8T 24T > Transfer Rate: 66.0MB/s 2.8MB/s 8.2MB/s 2.7MB/s > > -- > Cesar Eduardo Barros > cesarb@nitnet.com.br > cesarb@dcc.ufrj.br > - > To unsubscribe from this list: send the line "unsubscribe linux-kernel" in > the body of a message to majordomo@vger.kernel.org > Please read the FAQ at http://www.tux.org/lkml/ >
Andre Hedrick The Linux ATA/IDE guy
- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org Please read the FAQ at http://www.tux.org/lkml/
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