Messages in this thread |  | | Date | Fri, 25 Aug 2000 02:07:27 -0300 | Subject | UDMA trouble in VT82C586 IDE | From | Cesar Eduardo Barros <> |
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I'm having trouble making UDMA work with a FIC SD11 motherboard. After enabling via82cxxx tuning (or enabling UDMA "by hand" with hdparm), when a burst of IO happens I get errors like this (kernel 2.4.0-test7):
hda: timeout waiting for DMA ide_dmaproc: chipset supported ide_dma_timeout func only: 14 hda: irq timeout: status=0x58 { DriveReady SeekComplete DataRequest } hda: timeout waiting for DMA ide_dmaproc: chipset supported ide_dma_timeout func only: 14 hda: irq timeout: status=0xd0 { Busy } hda: DMA disabled ide0: reset: success
(this one was in the middle of the boot, while loading all daemons)
And it can't even see I'm using the UDMA66 cable (which the BIOS can see with no problem):
Uniform Multi-Platform E-IDE driver Revision: 6.31 ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx VP_IDE: IDE controller on PCI bus 00 dev 39 VP_IDE: chipset revision 6 VP_IDE: not 100% native mode: will probe irqs later ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx AMD IronGate Chipset Core ATA-66 Split FIFO Configuration: 8 Primary buffers, threshold = 1/2 8 Second. buffers, threshold = 1/2 ide0: BM-DMA at 0xffa0-0xffa7, BIOS settings: hda:DMA, hdb:pio ide0: VIA Bus-Master (U)DMA Timing Config Success ide1: BM-DMA at 0xffa8-0xffaf, BIOS settings: hdc:pio, hdd:pio ide1: VIA Bus-Master (U)DMA Timing Config Success hda: ST320423A, ATA DISK drive hdc: CR-2802TE, ATAPI CDROM drive ide0 at 0x1f0-0x1f7,0x3f6 on irq 14 ide1 at 0x170-0x177,0x376 on irq 15 hda: 40011300 sectors (20486 MB) w/512KiB Cache, CHS=2490/255/63, UDMA(33) Partition check: hda: hda1
/proc/ide/via says:
Command register = 0x7 Master Read Cycle IRDY 0 Wait State Master Write Cycle IRDY 0 Wait State FIFO Output Data 1/2 Clock Advance: off Bus Master IDE Status Register Read Retry: on Latency timer = 32 (max. = 0) Interrupt Steering Swap: off ------------------Primary IDE------------Secondary IDE----- both channels togth: yes yes Prefetch Buffer : on on Post Write Buffer: on on FIFO Conf/Chan. : 08 08 Threshold Prim. : 1/2 1/2 Read DMA FIFO flush: on on End Sect. FIFO flush: on on Max DRDY Pulse Width: No limitation Bytes Per Sector: 512 512 --------------drive0------drive1-------drive0------drive1---- DMA enabled: no no no no Act Pls Width: 03 11 04 11 Recovery Time: 01 09 02 09 Add. Setup T.: 4T 4T 4T 4T ------------------UDMA-Timing-Control------------------------ Enable Meth.: 1 0 0 0 Enable: yes no no no Transfer Mode: PIO DMA DMA DMA Cycle Time: 2T 5T 5T 5T
The drive is a ST320423A.
-- Cesar Eduardo Barros cesarb@nitnet.com.br cesarb@dcc.ufrj.br - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org Please read the FAQ at http://www.tux.org/lkml/
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