Messages in this thread | | | Date | Mon, 14 Aug 2000 00:18:49 +0200 (CEST) | From | Gérard Roudier <> | Subject | Re: A simple question about readw, readw and the like |
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On Thu, 3 Aug 2000, Jamie Lokier wrote:
> David S. Miller wrote: > > Strangely enough this is exactly what the drivers/scsi/ncr53c8xx.c > > driver (which I used as an example in a previous email) does too, so > > you can just steal the arch ifdef mania from there to get the > > necessary functionality. > > Speaking of which, this section of ncr53c8xx.c > > ** On x86 architecture, write buffers management does > ** not reorder writes to memory. So, using compiler > ** optimization barriers is enough to guarantee some > ** ordering when the CPU is writing data accessed by > ** the NCR. > ** On Alpha architecture, explicit memory barriers have > ** to be used. > ** Other architectures are defaulted to mb() macro if > ** defined, otherwise use compiler barrier. > > can be replaced by wmb() now, can't it?
You must be very careful when playing with partial (read|write) memory barriers. It is probably impossible to obtain such a semantic that applies equally to all architectures. For example, as described in the Alpha architecture Handbook, the Alpha WMB instruction (you seem to care about) is only required to insert a barrier for WRITEs that are targetted to the same kind of region (memory-like regions versus non memory-like regions).
As a result, the following scenario:
WA: WRITE A TO MEMORY WB: WRITE B TO MMIO WMB WC: WRITE C TO MEMORY WD: WRITE D TO MMIO
only ensures WA to precede WC and WB to precede WD, as seen by other agents on the system BUS. An agent seeing WB, WD, WA, WC is a quite legal situation here.
Basically, such a Write Barrier can only be used when a single kind of region is involved. This is rarely the case in driver/device pairs that support DMA.
Btw, speaking for myself I have properly decided to ignore partial barriers. IMO, situations where they make significant difference are probably pretty rare. Obviously, the WMB can be very useful for combining and flushing a batch of WRITEs to a frame buffer at a minimal cost but this is a no-DMA situation and ordering is less critical here than in DMA situations.
Speaking about the [sym|ncr]53c8xx drivers, there are some places where ordering is required for WRITEs targetting the both kinds of regions. For example when an IO is queued to the controller:
1) QUEUE the IO to the START QUEUE (this queue is in main memory and accessed by the device using DMA) 2) WRITE a FLAG to an IO REGISTER to tell the device about (MMIO)
"(1) then (2)" must not be reordered as seen by the PCI device. A WMB does not help here since (1) writes some data to memory and (2) writes data to MMIO (non memory-like).
Gerard.
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