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SubjectRe: i8259 IRQ problems
James Bottomley wrote:
> The IOAPIC polls its interrup lines sequentially. When it finds one active it
> sends a message on the APIC bus and starts polling at the next line up.
> Thus
> there is no priority ordering to interrupt line numbers in the IOAPIC. APIC
> bus arbitration is done by a priority ordering backoff scheme to try to ensure
> fair arbitration.

> CPUs can implement priority ordering in the local apic but
> currently don't.
Are you sure?
The Intel PPro documentation isn't very clear - but docu is never clear
about deficiencies of the product :-/

> A local APIC won't accept another interrupt while the CPU has interrupts
> disabled.
Are you sure?
The "Interrupt Acceptance Flow Chart for the Local APIC" doesn't contain
the "Interrupt Enabled" flag of the associated cpu.

> This means (under the linux scheme) that when you go into your
> interrupt handler, you cannot be interrupted by anything until you do a sti or
> reti.
arch/i386/kernel/irq.c:handle_IRQ_event() enables the interrupts very
early, far before we issue the EOI.

> > The task priority remains 0, but the local apic maintains a "Processor
> > priority register", and this one changes automagically.
> This register is used in the priority backoff algorithm on the APIC bus, not
> for interrupt priority.

This is wrong: the arbitration priority register APR is used for the
priority backoff.
The local APIC uses 3 priority registers [APR, PPR, TPR], plus an "Arb
ID" as a tie breaker.

Chapter (END-OF-INTERRUPT) is clearer:

[...EOI...]. This in an indication for the local APIC it can issue the
next interrupt, regardless of whether the current interrupt sercice has
been terminated or not. Note that interrupts whose priority is higher
than that currently in servce, do not wait for the EOI command
correspinging to the interrupt in service.


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