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SubjectRe: question about tulip patch to set CSR0 for pci 2.0 bus
On Sat, 9 Dec 2000, Alan Cox wrote:

> > Just in case you didn't catch it: this is not a PCI v2.0 vs. v2.1 issue.
> > The older Tulips work great with PCI v2.0 and v2.1. The bug is with longer
> > bursts and a specific i486 chipset/motherboard.
>
> Which chipset. I can then add it to the PCI quirks and we can do it nicely
> in 2.4 so that drivers can test the pci quirk list

I had the problem with the Intel Saturn II chipset used on the Asus SP3G.
The same problem was reported with the Saturn I on the SP3.

The bug manifests as occasional bus-master transfer data corruption.

The work-around was to change the Tulip PCI control register to use
8 longword cache alignment, 8 longword burst.
when the Tulip driver was run on a 486.

The old non-module work-around was
if (x86 <= 4)
printk(KERN_INFO "%s: This is a 386/486 PCI system, setting cache "
"alignment to %x.\n", dev->name,
0x01A00000 | (x86 <= 4 ? 0x4800 : 0x8000));

I removed this code and replaced with the ability to set the variable "csr0"
as a module option. There is no way to activate the fix with a built-in
driver.

Donald Becker becker@scyld.com
Scyld Computing Corporation http://www.scyld.com
410 Severn Ave. Suite 210 Second Generation Beowulf Clusters
Annapolis MD 21403 410-990-9993

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