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SubjectRe: Installing kernel 2.4


"Jeff V. Merkey" wrote:
>
> davej@suse.de wrote:
> >
> > > There are tests for all this in the feature flags for intel and
> > > non-intel CPUs like AMD -- including MTRR settings. All of this could
> > > be dynamic. Here's some code that does this, and it's similiar to
> > > NetWare. It detexts CPU type, feature flags, special instructions,
> > > etc. All of this on x86 could be dynamically detected.
> >
> > Detecting the CPU isn't the issue (we already do all this), it's what to
> > do when you've figured out what the CPU is. Show me code that can
> > dynamically adjust the alignment of the routines/variables/structs
> > dependant upon cacheline size.

ftp.timpanogas.org/manos/manos0817.tar.gz

Look in the PE loader -- Microsoft's PE loader can do this since
everything is RVA based. If you want to take the loader and put it in
Linux, be my guest. You can even combine mutiple i86 segments all
compiled under different options (or architectures) and bundle them into
a single executable file -- not somthing gcc can do today -- even with
DLL. This code is almost identical to the PE loader used in NT -- with
one exception, I omit the fs:_THREAD_DLS startup code...

8)

Jeff


>
> If the compiler always aligned all functions and data on 16 byte
> boundries (NetWare)
> for all i386 code, it would run a lot faster. Cache line alignment
> could be an option in the loader .... after all, it's hte loader that
> locates data in memory. If Linux were PE based, relocation logic would
> be a snap with this model (like NT).
>
> Jeff
>
> >
> > regards,
> >
> > Davej.
> >
> > --
> > | Dave Jones <davej@suse.de> http://www.suse.de/~davej
> > | SuSE Labs
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