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SubjectRe: FIXED! Updated 2.4 TODO List -- new addition WAS(test9 PCI resourcecollisions (fwd)
Hi Jeff!

> First, some definitions:
> downstream - away from the host processor
> primary - number of the PCI bus closer to the host processor
> secondary - number of the PCI bus on the downstream side of the PCI
> bridge
> subordinate - number of the highest-numbered bus on the downstream side
> of the PCI bridge


> > 00:03.0 CardBus bridge: Texas Instruments PCI1131 (rev 01)
> > Bus: primary=00, secondary=02, subordinate=05, sec-latency=0
> First bridge on bus 0.
> primary == 0 - ok
> secondary == 2, should be 1 (bus #1 is behind this bridge)

Why? Behind this bridge, there is bus #2, not bus #1. Bus #1 is behind the
PCI-to-PCI bridge 00:11.0.

> subordinate == 5, should be 2 (bus #2 follows us)

The bus numbers assigned by the current kernel may look strange, but they are
perfectly correct according to the definition above. The PCI specs don't enforce
any specific ordering of bridges on the same bus, the only requirements are that
that the secondary...subordinate ranges of the bridges don't overlap and that
they are in the secondary+1...subordinate range of the parent bus (which is
01...FF for the root bus).

> > 00:03.1 CardBus bridge: Texas Instruments PCI1131 (rev 01)
> > Bus: primary=00, secondary=06, subordinate=09, sec-latency=0
> > 00:11.0 PCI bridge: Intel Corporation 82380FB (rev 01) (prog-if 80)
> > Bus: primary=00, secondary=01, subordinate=01, sec-latency=0

This gives us the following assignment:

00 root bus (01-FF allowed for its sub-busses)
01 secondary PCI
02-05 first cardbus
06-09 second cardbus

which doesn't break the rules.

> Second, will anything break if bus numbers change on x86? There exists
> pcibios_assign_all_busses() on all platforms... but only Alpha defines
> it to 1. All others define it to zero.

Yes, it will break on any machine with multiple primary PCI busses, because
the registers assigning bus number ranges to primary busses are chipset

In 2.5, I'd like to rewrite the resource + bus number assignment code to be
able to re-layout the busses and resources even on i386 if it detects it's
safe to do so (that is there is either only one primary bus or the host bridge
is known). This will be needed for proper PCI hotplug and it will also help
us to get rid of some more BIOS bugs (especially on some embedded systems).

Have a nice fortnight
Martin `MJ' Mares <> <>
"Anyone can build a fast CPU. The trick is to build a fast system." -- S. Cray
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