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SubjectRe: Updated 2.4 TODO List -- new addition WAS(test9 PCI resource collisions (fwd)

On 24 Oct 2000, Eric W. Biederman wrote:
> "David S. Miller" <> writes:
> >
> > I bet PCI allows no such thing, thus to be totally safe I would
> > conditionalize this feature on the specific bridge. Ie. only allow
> > it for this bridge type, because I bet it is just some bug in the
> > the address comparators which makes the bridge interpret zero ranges
> > as "forward and respond to everything".
> I'm not certain of the details but I do know that it is legal.
> To date I've only heard of it on ISA bridges, in particular the PIIXE.

All ISA bridges use subtractive decode (== listen to whether somebody else
claims it, and if not, take it yourself), and that's part of the spec.

However, there can obviously be only one subtractive decoder on a bus:
otherwise they'd end up fighting over the requests that don't have anybody
on the primary bus.

HOWEVER, you could potentially have multiple subtractive decoders if you
have multiple buses, and that's actually kind of what my pseudo-patch
tries to allow for. I'd like to see what the lspci outout is, but it is
possible that the docking bridge is behind another PCI bridge, which would
make subtractive decoding legal.

The other alternative is that the docking bridge also is the ISA bridge,
and knows where the ISA space is (not that hard - ISA IO space is
0x100-0x3ff, and ISA memory space is basically limited to 0xA0000-1M now
that there are no machines with less than 16MB of RAM any more), and then
acts as _one_ subtractive bridge, but forwards it to two different buses
depending on what the range was.

So there does seem to be "legal" ways of doing what the bridge may be
doing. I'd still like to see what the PCI details on that system are, and
if possible get some documentation on that particular bridge to see what
that says..


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