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SubjectRe: test10-pre1 problems on 4-way SuperServer8050
On Thu, Oct 12, 2000 at 09:21:00AM +0100, Tigran Aivazian wrote:
> If MTRR support is disabled then both eepro100 interfaces work fine but
> the system is still 40x slower. This is the entire bootlog of
> 2.4.0-test10-pre1 + lspci-vvx + /proc/interrupts + /proc/iomem + ifconfig
> output
> Two currently active ideas (from Mark, Linus and Zoltan):
> b) this is an L2 cache-tag issue and there is just not enough bits in the
> tag to cover such high addresses so nothing will help, save removing the
> extra 2G or so out of the machine (or using them as MTD devices :(((( I
> hope this is _not_ the case...

Reminds me of the difference in between Celeron and XEON
variants of Pentium II -- Celerons can cache only the low
4 GB of address space, XEONs can cache whole 36 bits.

(Propably other differences exist also, but that is primary
one concerning memory cacheability --> apparent speed.)

> CPU0: Intel Pentium III (Cascades) stepping 01
> CPU1: Intel Pentium III (Cascades) stepping 01
> CPU2: Intel Pentium III (Cascades) stepping 01
> CPU3: Intel Pentium III (Cascades) stepping 01
> Total of 4 processors activated (5606.60 BogoMIPS).

Hmm.. More marketing names, what is "Cascades" in the scale
of "cheap bastards" versus "all bells and whistless" ?
(Celeron vs. XEON, that is.)

/Matti Aarnio
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