lkml.org 
[lkml]   [2000]   [Oct]   [10]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
Patch in this message
/
From
Date
SubjectRe: 2.4.0-test9 + Winchip2/2A processor family == hang on boot

> I tried the patch, but the result is the same... Uncompressing Linux...,
> now booting the kernel..., NOTHING....
> These Winchips need all the help they can get, so if you know something
> else I might try...

Ok, I've narrowed it down to the changes to mtrr.c in test8
Looks like the Cyrix III changes broke things.
Didn't something similar happen when these changes made it into
a 2.2.18pre ? Alan?

For now reverse the diff below by patching with -R
I'll take a look at a proper fix after lectures later today[1]..
unless someone else spots the error in the meantime.

regards,

Dave.

[1] Why do all the fun things happen on my busiest days ? :)

--
| Dave Jones <davej@suse.de> http://www.suse.de/~davej
| SuSE Labs


diff -u --recursive --new-file v2.4.0-test8/linux/arch/i386/kernel/mtrr.c linux/arch/i386/kernel/mtrr.c
--- v2.4.0-test8/linux/arch/i386/kernel/mtrr.c Wed Jul 12 21:58:41 2000
+++ linux/arch/i386/kernel/mtrr.c Sun Oct 1 20:35:15 2000
@@ -319,10 +319,10 @@
#endif

#ifdef USERSPACE_INTERFACE
-static char *ascii_buffer = NULL;
-static unsigned int ascii_buf_bytes = 0;
+static char *ascii_buffer;
+static unsigned int ascii_buf_bytes;
#endif
-static unsigned int *usage_table = NULL;
+static unsigned int *usage_table;
static DECLARE_MUTEX(main_lock);

/* Private functions */
@@ -356,7 +356,8 @@
if (boot_cpu_data.x86 >= 6) break; /* Athlon and post-Athlon CPUs */
/* else fall through */
case X86_VENDOR_CENTAUR:
- return;
+ if(boot_cpu_data.x86 != 6)
+ return;
/*break;*/
}
/* Save value of CR4 and clear Page Global Enable (bit 7) */
@@ -380,6 +381,7 @@
{
case X86_VENDOR_AMD:
case X86_VENDOR_INTEL:
+ case X86_VENDOR_CENTAUR:
/* Disable MTRRs, and set the default type to uncached */
rdmsr (MTRRdefType_MSR, ctxt->deftype_lo, ctxt->deftype_hi);
wrmsr (MTRRdefType_MSR, ctxt->deftype_lo & 0xf300UL, ctxt->deftype_hi);
@@ -403,8 +405,11 @@
if (boot_cpu_data.x86 >= 6) break; /* Athlon and post-Athlon CPUs */
/* else fall through */
case X86_VENDOR_CENTAUR:
- __restore_flags (ctxt->flags);
- return;
+ if(boot_cpu_data.x86 != 6)
+ {
+ __restore_flags (ctxt->flags);
+ return;
+ }
/*break;*/
}
/* Flush caches and TLBs */
@@ -415,6 +420,7 @@
{
case X86_VENDOR_AMD:
case X86_VENDOR_INTEL:
+ case X86_VENDOR_CENTAUR:
wrmsr (MTRRdefType_MSR, ctxt->deftype_lo, ctxt->deftype_hi);
break;
case X86_VENDOR_CYRIX:
@@ -453,9 +459,17 @@
/*break;*/
case X86_VENDOR_CYRIX:
/* Cyrix have 8 ARRs */
+ return 8;
case X86_VENDOR_CENTAUR:
/* and Centaur has 8 MCR's */
- return 8;
+ if(boot_cpu_data.x86==5)
+ return 8;
+ /* the cyrix III has intel compatible MTRR */
+ if(boot_cpu_data.x86==6)
+ {
+ rdmsr (MTRRcap_MSR, config, dummy);
+ return (config & 0xff);
+ }
/*break;*/
}
return 0;
@@ -471,12 +485,15 @@
case X86_VENDOR_AMD:
if (boot_cpu_data.x86 < 6) return 1; /* pre-Athlon CPUs */
/* else fall through */
+ case X86_VENDOR_CENTAUR:
+ if (boot_cpu_data.x86 == 5)
+ return 1; /* C6 */
+ /* CyrixIII is Intel like */
case X86_VENDOR_INTEL:
rdmsr (MTRRcap_MSR, config, dummy);
return (config & (1<<10));
/*break;*/
case X86_VENDOR_CYRIX:
- case X86_VENDOR_CENTAUR:
return 1;
/*break;*/
}
@@ -623,7 +640,7 @@
} /* End Function centaur_get_mcr */

static void (*get_mtrr) (unsigned int reg, unsigned long *base,
- unsigned long *size, mtrr_type *type) = NULL;
+ unsigned long *size, mtrr_type *type);

static void intel_set_mtrr_up (unsigned int reg, unsigned long base,
unsigned long size, mtrr_type type, int do_safe)
@@ -766,7 +783,7 @@

static void (*set_mtrr_up) (unsigned int reg, unsigned long base,
unsigned long size, mtrr_type type,
- int do_safe) = NULL;
+ int do_safe);

#ifdef CONFIG_SMP

@@ -1194,7 +1211,7 @@
printk ("mtrr: size: %lx base: %lx\n", size, base);
return -EINVAL;
}
- if (boot_cpu_data.x86_vendor == X86_VENDOR_CENTAUR)
+ if (boot_cpu_data.x86_vendor == X86_VENDOR_CENTAUR && boot_cpu_data.x86 == 5)
{
if (type != MTRR_TYPE_WRCOMB)
{
@@ -1779,8 +1796,16 @@
get_free_region = cyrix_get_free_region;
break;
case X86_VENDOR_CENTAUR:
- get_mtrr = centaur_get_mcr;
- set_mtrr_up = centaur_set_mcr_up;
+ if(boot_cpu_data.x86 == 5)
+ {
+ get_mtrr = centaur_get_mcr;
+ set_mtrr_up = centaur_set_mcr_up;
+ }
+ if(boot_cpu_data.x86 == 6)
+ {
+ get_mtrr = intel_get_mtrr;
+ set_mtrr_up = intel_set_mtrr_up;
+ }
break;
}
} /* End Function mtrr_setup */
@@ -1804,8 +1829,11 @@
case X86_VENDOR_CYRIX:
cyrix_arr_init ();
break;
- case X86_VENDOR_CENTAUR:
- centaur_mcr_init ();
+ case X86_VENDOR_CENTAUR: /* C6 and Cyrix III have different ones */
+ if(boot_cpu_data.x86 == 5)
+ centaur_mcr_init ();
+ if(boot_cpu_data.x86 == 6)
+ get_mtrr_state(&smp_mtrr_state);
break;
}
} /* End Function mtrr_init_boot_cpu */
@@ -1877,7 +1905,8 @@
cyrix_arr_init ();
break;
case X86_VENDOR_CENTAUR:
- centaur_mcr_init ();
+ if(boot_cpu_data.x86 == 5)
+ centaur_mcr_init ();
break;
}
#endif /* !CONFIG_SMP */

-
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@vger.kernel.org
Please read the FAQ at http://www.tux.org/lkml/

\
 
 \ /
  Last update: 2005-03-22 12:39    [W:0.039 / U:2.580 seconds]
©2003-2018 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site