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SubjectRe: kernel thread support - LWP's
On Thu, Jul 15, 1999 at 05:07:23PM -0600, Larry McVoy wrote:
> : Now you can say that a real app will swamp this with cache misses. But
> : when it's within the cache, ~2-3 microseconds kernel vs. 0.05
> : microseconds user is a pretty severe difference.
>
> Really? I doubt it. I understand the need I just think he's going about it
> wrong. If what you want is low latency packet transfers, the fastest way
> is no context switch at all. The device should place the data in memory and
> you should be sitting there waiting for it.

Steve Pink and other authors forgotten due to old age have this wonderful
router design where one processor of a dual runs a BSD variant and the
other runs a dedicated _polling_ router in the L2 cache using a compressed
routing table. If the dedicated router can't figure out what to do with
a message, it passes it to BSD. No interrupts, no cache misses, no OS
delays. One of the nice things about this design is it is based on a
clear understanding that you can't get something for nothing: no OS
structuring technique is going to make TCP/IP code perform like
raw ethernet packet code.



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