Messages in this thread | | | From | "Stefan Monnier" <monnier+lists/linux/kernel/news/@tequila.cs.yale.edu> | Subject | Re: EPIC | Date | 06 Jun 1999 14:52:51 -0400 |
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>>>>> "David" == David S Miller <davem@redhat.com> writes: > Thus, if the UltraSparc I-cache has been pushing 16bytes per clock for > a few years now, I am very sure 32bytes per clock from some cpu vendor > is just around the corner. :-)
PowerPC-601 (aka the very first PowerPC) already had such a 8x32bit bus between the cache and the CPU. It was done this way because the cache was shared between instruction and data, so by reading 8 insts at a time, the cache was more often available for data accesses.
Stefan
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