Messages in this thread | | | Date | Sun, 6 Jun 1999 09:08:28 -0700 | From | "David S. Miller" <> | Subject | Re: EPIC |
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Date: Sun, 6 Jun 1999 18:31:10 +0300 From: Matti Aarnio <matti.aarnio@sonera.fi>
The instruction format expects 3+1 longwords (32-bits each) worth of instruction stream data, and although its ways to explicitely combine integer and float instructions are more versatile (=complicated) than what DEC 21264 Alpha can do, it can barely match said Alpha processor in speed of instructions per clock cycle. (That alpha can do up to 2i+2fp instructions per clock.)
You have precluded the possibility of dispatching multiple bundles per clock cycle, and I am rather sure this will be a characteristic of various EPIC processors. Especially because the bundling simplifies the multi-issue logic in the instruction prefetcher (one possible implementation could be to compress the bit patterns of the bundle types into some "hash key" like code, and use CAM memory to lookup the decision of which of the bundles can be sent in parallel to the execution units, and perhaps also _which_ execution units).
If people want my own personal opinion about this chips design (too bad, you're going to get it anyways :-) I view it as a set of powerful core ideas (most likely from the HP camp) with several terrible hacks thrown on top (which, if not done by HP... :-)
Later, David S. Miller davem@redhat.com
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