Messages in this thread | | | Date | Sun, 16 May 1999 16:07:00 +0200 | From | (Tor Arntsen) | Subject | Re: Alpha Timekeeping - Hardware Questions |
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Matti Aarnio <matti.aarnio@sonera.fi> writes: > I have never heard of actual instances of multiprocessor systems > where processors run at different clock speeds, even if that were > technically possible by decoupling CPU internal operations, and > external system bus.
#hinv | agrep 'Processor|CPU|Secon' Processor 0: 150 MHZ IP19 CPU: MIPS R4400 Processor Chip Revision: 5.0 Processor 1: 150 MHZ IP19 CPU: MIPS R4400 Processor Chip Revision: 5.0 Processor 2: 200 MHZ IP19 CPU: MIPS R4400 Processor Chip Revision: 6.0 Processor 3: 200 MHZ IP19 CPU: MIPS R4400 Processor Chip Revision: 6.0 Secondary unified instruction/data cache size: 1 Mbyte Secondary unified instruction/data cache size: 1 Mbyte Secondary unified instruction/data cache size: 4 Mbytes Secondary unified instruction/data cache size: 4 Mbytes
SGI Challenge-L.
- Tor
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