lkml.org 
[lkml]   [1999]   [May]   [16]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
/
Date
From
SubjectRe: Alpha Timekeeping - Hardware Questions
Matti Aarnio <matti.aarnio@sonera.fi> writes:
> I have never heard of actual instances of multiprocessor systems
> where processors run at different clock speeds, even if that were
> technically possible by decoupling CPU internal operations, and
> external system bus.

#hinv | agrep 'Processor|CPU|Secon'
Processor 0: 150 MHZ IP19
CPU: MIPS R4400 Processor Chip Revision: 5.0
Processor 1: 150 MHZ IP19
CPU: MIPS R4400 Processor Chip Revision: 5.0
Processor 2: 200 MHZ IP19
CPU: MIPS R4400 Processor Chip Revision: 6.0
Processor 3: 200 MHZ IP19
CPU: MIPS R4400 Processor Chip Revision: 6.0
Secondary unified instruction/data cache size: 1 Mbyte
Secondary unified instruction/data cache size: 1 Mbyte
Secondary unified instruction/data cache size: 4 Mbytes
Secondary unified instruction/data cache size: 4 Mbytes

SGI Challenge-L.

- Tor


-
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@vger.rutgers.edu
Please read the FAQ at http://www.tux.org/lkml/

\
 
 \ /
  Last update: 2005-03-22 13:51    [W:0.034 / U:0.068 seconds]
©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site