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Subjectmmap() 'Page Cache Disable' and 'Page Write Through'
Hi All,

After some discussion on the XFree86 development list, and lots of
screwing around under 32-bit DOS (to test my ring 0 code easily ;-),
I have discovered some strange anomolies in the handling of physical
memory mappings combined with the Pentium Pro/II/III MTRR support.
Specifically:

1. If the Page Cache Disable (PCD) *and* Page Write Though (PWT)
bits of the page table entry are set, the effects of write
combining enabled via the MTRR region are disabled.

2. If the Page Cache Disable (PCD) is set but the Page Write Though
(PWT) bit is not, the write combining enabled via the MTRR region
works the same as if none of the bits are set.

3. The Linux kernel only ever sets the PCD bit, and never sets the
PWT bit. If the PCD bit is set for i486 and Pentium processors,
caching is disable for those pages.

The Page Cache Disable bit is important for i486 and Pentium
processors because that is the only mechanism that can be used to
disable caching for MMIO register regions. This is used in the Linux
kernel (mmap_mem.c I believe) and the comments mention that this is
needed because of problems reported by the XFree86 team.

However because the PWT bit is never set, if a BIOS has enabled write
combining for the framebuffer of a graphics card *and* that graphics
card has the MMIO registers mapped at the end of the framebuffer
(Tseng ET6000 and ATI cards are prime examples), then the MMIO
registers get cached write combined which causes problems.

One solution to this problelm is to use an overlapping MTRR region to
disable write combining for the MMIO registers, which is what XFree86
4.0 will be doing. However this has significant drawbacks for a
number of reasons:

1. In multi-controller environments we will quickly run out of MTRR
registers even on Intel processors (that currently have 8 total)
because we will need at least two for each device (possibly up to
3).

2. Other processors such as the Cyrix and AMD have far fewer MTRR's
(AMD only has two I believe), and hence this solution will not
work for those processors.

3. MTRR's may want to be used by other devices for improved
performance.

Hence it would be much better if the Linux kernel could allocate
mappings via mmap() with the PCD *and* PWT bits set, but only do this
if the caller actually needs this (ie: doing this for the framebuffer
mapping is not desireable!). One way to do this, is to change the
kernel so that if the /dev/mem device is opened with O_SYNC it will
set both the PCD and PWT bits. If it is opened without O_SYNC, it
will ony set the PCD bit (for backwards compatibility with older i486
and Pentium systems).

Comments?


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