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SubjectRe: 2.2.5 optimizations for web benchmarks?

On 30 Apr 1999, Linus Torvalds wrote:

> If they indeed do it in three cycles without a stall, that's a
> surprisingly _huge_ improvement for them. [...]

i have to correct my statement, the true cost is 5 cycles, and this likely
includes a pipeline stall. I've attached some code that tries to carefully
measure the cost of cached TLB misses. (it generates a random access
pattern, then it measures the cost of reading pages randomly from a big
buffer) The numbers when accessing 512 pages randomly are:

[root@moon asm]# ./tlb
6 1 6 6 6 6 6 6 6 6 1 1 6 6 6 6 6 6 6 6 6 6 6 6 1 1 6 6 6 6 6 6 6 6 6 6 6
6 6 6 1 1 6 6 6 6 6 6 6 6 1 6 6 6 6 6 6 6 6 1 6 6 6 6 6 6 6 6 6 6 6 6 6 6
6 6 1 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 1 6 6 6 6 6 6 6 1 6 6 6 6 6 6 6 6
6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 1 6 6 6 6 6 6 6 6 6 1 6 1 6 6 6 6 6 6 6 6 6
6 6 6 6 6 6 6 6 6 6 6 6 6 6 1 6 6 1 6 6 6 6 6 6 6 6 6 6 6 6 6 1 6 6 6 6 6
6 6 6 6 6 6 6 6 6 6 1 6 1 6 6 6 6 6 6 6 6 1 6 6 6 6 6 1 6 6 6 6 6 1 6 6 6
6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 1 6 6 6 6 6 6 6 6 6 6 6 1 6 6 6 6 6 6 1 6
6 6 6 6 6 6 6 6 6 6 6 6 6 6 1 6 6 6 1 1 6 6 6 6 6 6 6 6 6 6 6 6 1 6 6 6 6
6 6 6 6 6 6 6 6 6 1 6 6 6 6 6 1 6 6 6 1 6 6 6 1 6 6 6 6 1 1 6 6 6 6 1 6 6
6 1 6 6 6 6 6 6 6 6 6 6 1 1 6 6 6 6 6 1 6 6 6 6 6 6 6 6 1 6 6 6 1 6 6 6 6
6 6 6 6 6 1 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6
6 6 6 6 6 6 6 6 1 6 1 6 1 6 6 6 6 6 6 6 6 6 6 6 6 6 1 6 6 6 6 6 6 6 6 6 6
6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 1 6 6 6 6 1 6 6 6 6 1 6 6 6 6 6 6 6 1 6
1 6 6 6 6 1 1 6 6 6 6 6 6 6 6 6 6 6 6 1 6 6 6 6 6 6 6 6 6 1 6
512 randomly accessed pages, 88.867188% TLB misses.
[root@moon asm]#

ie. 1 cycle when no TLB miss memory access, 6 cycles when memory access +
TLB miss. (The 3 cycles claim came from a flawed variant of this test that
did not try to isolate rdtsc from the measured instructions ...)

and when accessing 32 pages (well below their TLB size) we get:

[root@moon asm]# ./tlb
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
32 randomly accessed pages, 0.000000% TLB misses.
[root@moon asm]#

sorry for spreading misinformation, TLB miss costs are still far from
being zero.

-- mingo
/*
* TLB miss measurement on PII CPUs.
*/
#include <stdio.h>
#include <stdlib.h>
#include <signal.h>
#include <sys/wait.h>
#include <linux/unistd.h>

#define BYTES (512*4*1024)
#define PAGES (BYTES/4096)

static char buffer[BYTES+1];
unsigned long long t1, t2, delta[PAGES];


void do_test (char * addr)
{
/*
* 'cli' is used as a serializing instruction to
* isolate the benchmarked instruction from rdtsc.
*/
__asm__ (
"
cli;
rdtsc;
movl %%eax, %%ebx;
movl %%edx, %%ecx;
cli;
# start of benchmarked section

movl (%%esi), %%eax;

# end of benchmarked section
cli;
rdtsc
sti;
"

:"=a" (*(((int*)&t2)+0)), "=d" (*(((int*)&t2)+1)),
"=b" (*(((int*)&t1)+0)), "=c" (*(((int*)&t1)+1))

:"S"(addr):"memory");
}

extern int iopl(int);

void main (void)
{
int j, k, c, hit;
int matrix [PAGES];

iopl(3);
/*
* first generate a random access pattern.
*/
for (j = 0; j < PAGES; j++) {
matrix[j] = random()/(RAND_MAX/PAGES);
if (matrix[j] >= PAGES)
printf("%d ", matrix[j]);
}

/*
* 10 warmup loops, the last one is printed.
*/
for (k = 0; k < 10; k++) {
c = 0;
for (j = 0; j < PAGES; j++) {
char * addr;
addr = buffer + matrix[j]*4096;
do_test(addr);
delta[c++] = t2-t1;
}
}
hit = 0;
for (j = 0; j < PAGES; j++) {
unsigned long long d = delta[j]-47;
printf("%Ld ", d);
if (d == 1)
hit++;
}
printf("\n");
printf("%d randomly accessed pages, %f%% TLB misses.\n", PAGES,
100.0*((double)PAGES-(double)hit)/(double)PAGES);
}

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