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SubjectRe: K6-2, Stepping 12, MTRR in 2.2.6
Jeff Epler writes:
> On Mon, Apr 19, 1999 at 12:45:20PM +1000, Richard Gooch wrote:
> > Linus' kernels don't have MTRR support for Cyrix or AMD. Grab my MTRR
> > patch from: http://www.atnf.csiro.au/~rgooch/linux/kernel-patches.html
> >
> > This has been submitted to Linus. I'm waiting for his comments.
>
> In the meantime, I notice that Alan has put an incompatible version
> of the mtrr patch into 6-ac1. What are the differences between
> these two implementations of mtrrs for AMD processors, and is a
> merged version in the works? The -ac1 version doesn't seem to work
> at all on my machine, /proc/mtrr exists but doesn't change when I
> "echo" to it.

Alan hacked the MTRR driver in the official tree some time after I
wrote a patch which re-organised the MTRR driver to cleanly support
non-Intel MTRRs. I wrote the patch because I was being sent patches
for Cyrix MTRR (ARR) support by Zoltan Boszormenyi. I then noticed
Alan had added AMD MTRr support in his patches, so I contacted him.
We agreed that his changes would be merged into my patch which would
eventually make it into Linus' tree.

So, my patch has code for AMD MTRRs which is based on Alan's patch,
although the structure is different because the AMD code is now just
one "driver" amongst others (Intel and Cyrix), rather than a straight
hack.

> By the way, I've missed the discussions, AMD seems to offer just two
> MTRRs. But I'd like to set up at least 3 distinct regions (main
> memory, 2d framebuffer, and voodoo2 memory). I suppose I just give
> up and do only main memory and 2d framebuffer. Should I do
> something complicated like changing the second mtrr to the voodoo2
> card when a mesa app starts up, and restoring it when it ends?

Yep, AMD has only two MTRRs. Bugger. I don't know if we can do
anything (other than suggest a better CPU:-). You could help us by
benchmarking which region is more useful to set to write-combining.
We can then put it in a FAQ.

One trick: if the FB and voodoo2 memory are contiguous (or at least,
nothing sits between them), you could make a single MTRR region which
covers both. If you're paranoid, you can use the PCD and PWT bits in
the page tables to turn off write-combining in the intervening region.

Regards,

Richard....

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