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SubjectRe: bad lmbench numbers for mmap
David Miller wrote:
> Yes do have to clear them, for two reasons:
> 1) So that the hardware MMU doesn't see valid entries after the
> tlb flush. (or in the case of clever software TLB miss strategies
> like that implemeted in the Alpha PAL code or in our sparc64 port,
> making sure the virtual page table mappings go away properly too)

In the hardware case, this isn't true (correct me) if you flush the TLB
after clearing the page directory entries, surely?

> 2) For the sake of the page table caching we do on all ports now.
> For #2, if a page table chunk is cached, it works so efficiently
> because it knows the chunks have been cleared out by the callers at
> some point before being free'd.

Point taken. #2 means nothing would be gained. (Unless clearing a
whole page is faster than clearing one pte at a time..)

-- Jamie

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