Messages in this thread Patch in this message | | | Date | Thu, 30 Dec 1999 03:45:01 +0000 (GMT) | From | Dave Jones <> | Subject | [PATCH] x86 setup code cleanup. |
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Hi all, For review, here's a patch against arch/i386/kernel/setup.c from 2.3.35
o Added intel_model() This makes identify_cpu() a more readable, and cuts out some checks for X86_VENDOR_INTEL o Improved Intel Celeron type identification Generated code should now do one less compare. [This code untested, Celeron owners, please check /proc/cpuinfo] o Intel Pentium 3 PSN uses a combined 'if' rather than two seperates. o identify_cpu() now uses a switch rather than lots of if's. Much more readable, and cleaner. o get_cpuinfo() now just checks the vendor, no longer the model. If a CPU doesn't support a feature, it won't get put into /proc/cpuinfo anyhow. o White space cleanup
Comments?
-- Dave.. --- setup.c.orig Wed Dec 29 22:45:22 1999 +++ setup.c Thu Dec 30 01:40:51 1999 @@ -204,7 +204,7 @@ */ outb_p(SIO_DEV_SEL, SIO_INDEX); outb_p(SIO_GP_DEV, SIO_DATA); /* Talk to GPIO regs. */ - + outb_p(SIO_DEV_MSB, SIO_INDEX); outb_p(SIO_GP_MSB, SIO_DATA); /* MSB of GPIO base address */ @@ -213,7 +213,7 @@ outb_p(SIO_DEV_ENB, SIO_INDEX); outb_p(1, SIO_DATA); /* Enable GPIO registers. */ - + /* * Now, we have to map the power management section to write * a bit which enables access to the GPIO registers. @@ -224,19 +224,19 @@ outb_p(SIO_DEV_MSB, SIO_INDEX); outb_p(SIO_PM_MSB, SIO_DATA); /* MSB of PM base address */ - + outb_p(SIO_DEV_LSB, SIO_INDEX); outb_p(SIO_PM_LSB, SIO_DATA); /* LSB of PM base address */ outb_p(SIO_DEV_ENB, SIO_INDEX); outb_p(1, SIO_DATA); /* Enable PM registers. */ - + /* * Now, write the PM register which enables the GPIO registers. */ outb_p(SIO_PM_FER2, SIO_PM_INDEX); outb_p(SIO_PM_GP_EN, SIO_PM_DATA); - + /* * Now, initialize the GPIO registers. * We want them all to be inputs which is the @@ -381,13 +381,13 @@ void __init add_memory_region(unsigned long start, - unsigned long size, int type) + unsigned long size, int type) { int x = e820.nr_map; if (x == E820MAX) { - printk("Ooops! Too many entries in the memory map!\n"); - return; + printk("Ooops! Too many entries in the memory map!\n"); + return; } e820.map[x].addr = start; @@ -718,9 +718,9 @@ } else { printk("initrd extends beyond end of memory " - "(0x%08lx > 0x%08lx)\ndisabling initrd\n", - INITRD_START + INITRD_SIZE, - max_low_pfn << PAGE_SHIFT); + "(0x%08lx > 0x%08lx)\ndisabling initrd\n", + INITRD_START + INITRD_SIZE, + max_low_pfn << PAGE_SHIFT); initrd_start = 0; } } @@ -893,16 +893,16 @@ cli(); ccr3 = getCx86(CX86_CCR3); setCx86(CX86_CCR3, ccr3 ^ 0x80); - getCx86(0xc0); /* dummy to change bus */ + getCx86(0xc0); /* dummy to change bus */ - if (getCx86(CX86_CCR3) == ccr3) { /* no DEVID regs. */ + if (getCx86(CX86_CCR3) == ccr3) { /* no DEVID regs. */ ccr2 = getCx86(CX86_CCR2); setCx86(CX86_CCR2, ccr2 ^ 0x04); getCx86(0xc0); /* dummy */ if (getCx86(CX86_CCR2) == ccr2) /* old Cx486SLC/DLC */ *dir0 = 0xfd; - else { /* Cx486S A step */ + else { /* Cx486S A step */ setCx86(CX86_CCR2, ccr2); *dir0 = 0xfe; } @@ -949,8 +949,8 @@ do_cyrix_devid(&dir0, &dir1); - Cx86_dir0_msb = dir0_msn = dir0 >> 4; /* identifies CPU "family" */ - dir0_lsn = dir0 & 0xf; /* model or clock multiplier */ + Cx86_dir0_msb = dir0_msn = dir0 >> 4; /* identifies CPU "family" */ + dir0_lsn = dir0 & 0xf; /* model or clock multiplier */ /* common case step number/rev -- exceptions handled below */ c->x86_model = (dir1 >> 4) + 1; @@ -986,7 +986,7 @@ Cx86_cb[0] = 'L'; p = Cx86_cb; (c->x86_model)++; - } else /* 686 */ + } else /* 686 */ p = Cx86_cb+1; /* Emulate MTRRs using Cyrix's ARRs. */ c->x86_capability |= X86_FEATURE_MTRR; @@ -1014,8 +1014,7 @@ get_model_name(c); /* get CPU marketing name */ c->x86_capability&=~X86_FEATURE_TSC; return; - } - else { /* MediaGX */ + } else { /* MediaGX */ Cx86_cb[2] = (dir0_lsn & 1) ? '3' : '4'; p = Cx86_cb+2; c->x86_model = (dir1 & 0x20) ? 1 : 2; @@ -1023,13 +1022,13 @@ } break; - case 5: /* 6x86MX/M II */ - if (dir1 > 7) dir0_msn++; /* M II */ - else c->coma_bug = 1; /* 6x86MX, it has the bug. */ - tmp = (!(dir0_lsn & 7) || dir0_lsn & 1) ? 2 : 0; + case 5: /* 6x86MX/M II */ + if (dir1 > 7) dir0_msn++; /* M II */ + else c->coma_bug = 1; /* 6x86MX, it has the bug. */ + tmp = (!(dir0_lsn & 7) || dir0_lsn & 1) ? 2 : 0; Cx86_cb[tmp] = cyrix_model_mult2[dir0_lsn & 7]; p = Cx86_cb+tmp; - if (((dir1 & 0x0f) > 4) || ((dir1 & 0xf0) == 0x20)) + if (((dir1 & 0x0f) > 4) || ((dir1 & 0xf0) == 0x20)) (c->x86_model)++; /* Emulate MTRRs using Cyrix's ARRs. */ c->x86_capability |= X86_FEATURE_MTRR; @@ -1179,78 +1178,53 @@ static struct cpu_model_info cpu_models[] __initdata = { { X86_VENDOR_INTEL, 4, { "486 DX-25/33", "486 DX-50", "486 SX", "486 DX/2", "486 SL", - "486 SX/2", NULL, "486 DX/2-WB", "486 DX/4", "486 DX/4-WB", NULL, - NULL, NULL, NULL, NULL, NULL }}, + "486 SX/2", NULL, "486 DX/2-WB", "486 DX/4", "486 DX/4-WB", NULL, + NULL, NULL, NULL, NULL, NULL }}, { X86_VENDOR_INTEL, 5, { "Pentium 60/66 A-step", "Pentium 60/66", "Pentium 75 - 200", - "OverDrive PODP5V83", "Pentium MMX", NULL, NULL, - "Mobile Pentium 75 - 200", "Mobile Pentium MMX", NULL, NULL, NULL, - NULL, NULL, NULL, NULL }}, + "OverDrive PODP5V83", "Pentium MMX", NULL, NULL, + "Mobile Pentium 75 - 200", "Mobile Pentium MMX", NULL, NULL, NULL, + NULL, NULL, NULL, NULL }}, { X86_VENDOR_INTEL, 6, { "Pentium Pro A-step", "Pentium Pro", NULL, "Pentium II (Klamath)", - NULL, "Pentium II (Deschutes)", "Mobile Pentium II", "Pentium III (Katmai)", - "Pentium III (Coppermine)", NULL, NULL, NULL, NULL, NULL, NULL }}, + NULL, "Pentium II (Deschutes)", "Mobile Pentium II", "Pentium III (Katmai)", + "Pentium III (Coppermine)", NULL, NULL, NULL, NULL, NULL, NULL }}, { X86_VENDOR_AMD, 4, { NULL, NULL, NULL, "486 DX/2", NULL, NULL, NULL, "486 DX/2-WB", - "486 DX/4", "486 DX/4-WB", NULL, NULL, NULL, NULL, "Am5x86-WT", - "Am5x86-WB" }}, + "486 DX/4", "486 DX/4-WB", NULL, NULL, NULL, NULL, "Am5x86-WT", + "Am5x86-WB" }}, { X86_VENDOR_AMD, 5, { "K5/SSA5", "K5", - "K5", "K5", NULL, NULL, - "K6", "K6", "K6-2", - "K6-3", NULL, NULL, NULL, NULL, NULL, NULL }}, + "K5", "K5", NULL, NULL, + "K6", "K6", "K6-2", + "K6-3", NULL, NULL, NULL, NULL, NULL, NULL }}, { X86_VENDOR_AMD, 6, { "Athlon", "Athlon", - NULL, NULL, NULL, NULL, - NULL, NULL, NULL, - NULL, NULL, NULL, NULL, NULL, NULL, NULL }}, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, + NULL, NULL, NULL, NULL, NULL, NULL, NULL }}, { X86_VENDOR_UMC, 4, { NULL, "U5D", "U5S", NULL, NULL, NULL, NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL, NULL, NULL }}, + NULL, NULL, NULL, NULL, NULL, NULL }}, { X86_VENDOR_NEXGEN, 5, { "Nx586", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL, NULL, NULL, NULL }}, + NULL, NULL, NULL, NULL, NULL, NULL, NULL }}, }; -void __init identify_cpu(struct cpuinfo_x86 *c) + +static void __init intel_model(struct cpuinfo_x86 *c) { int i; char *p = NULL; - c->loops_per_sec = loops_per_sec; - c->x86_cache_size = -1; - - get_cpu_vendor(c); - - if (c->x86_vendor == X86_VENDOR_UNKNOWN && - c->cpuid_level < 0) - return; - - if (c->x86_vendor == X86_VENDOR_CYRIX) { - cyrix_model(c); - return; - } - - if (c->x86_vendor == X86_VENDOR_AMD && amd_model(c)) - return; - - if (c->x86_vendor == X86_VENDOR_CENTAUR) { - centaur_model(c); - return; - } - - if (c->cpuid_level > 0 && c->x86_vendor == X86_VENDOR_INTEL) - { - if(c->x86_capability&(1<<18)) - { - /* Disable processor serial number on Intel Pentium III - from code by Phil Karn */ - unsigned long lo,hi; - rdmsr(0x119,lo,hi); - lo |= 0x200000; - wrmsr(0x119,lo,hi); - printk(KERN_INFO "Pentium-III serial number disabled.\n"); - } + if (c->cpuid_level > 0 && c->x86_capability&(1<<18)) { + /* Disable processor serial number on Intel Pentium III + from code by Phil Karn */ + unsigned long lo,hi; + rdmsr(0x119,lo,hi); + lo |= 0x200000; + wrmsr(0x119,lo,hi); + printk(KERN_INFO "Pentium-III serial number disabled.\n"); } if (c->cpuid_level > 1) { @@ -1296,21 +1270,21 @@ for (i = 0; i < sizeof(cpu_models)/sizeof(struct cpu_model_info); i++) { if (cpu_models[i].vendor == c->x86_vendor && - cpu_models[i].x86 == c->x86) { + cpu_models[i].x86 == c->x86) { if (c->x86_model <= 16) p = cpu_models[i].model_names[c->x86_model]; /* Names for the Pentium II Celeron processors - detectable only by also checking the cache size */ - if ((cpu_models[i].vendor == X86_VENDOR_INTEL) - && (cpu_models[i].x86 == 6)) - { - if(c->x86_model == 5 && c->x86_cache_size == 0) - p = "Celeron (Covington)"; - else if(c->x86_model == 6 && c->x86_cache_size == 128) - p = "Celeron (Mendocino)"; - else if(c->x86_model == 5 && c->x86_cache_size == 256) - p = "Celeron (Dixon)"; + detectable only by also checking the cache size */ + if (cpu_models[i].x86 == 6) { + if (c->x86_model == 5) { + if (c->x86_cache_size==0) + p = "Celeron (Covington)"; + if (c->x86_cache_size==256) + p = "Celeron (Dixon)"; + } + if (c->x86_model == 6 && c->x86_cache_size == 128) + p = "Celeron (Mendocino)"; } } } @@ -1323,6 +1297,38 @@ sprintf(c->x86_model_id, "%02x/%02x", c->x86_vendor, c->x86_model); } + +void __init identify_cpu(struct cpuinfo_x86 *c) +{ + c->loops_per_sec = loops_per_sec; + c->x86_cache_size = -1; + + get_cpu_vendor(c); + + switch (c->x86_vendor) { + case X86_VENDOR_UNKNOWN: + break; + + case X86_VENDOR_INTEL: + intel_model(c); + break; + + case X86_VENDOR_CYRIX: + cyrix_model(c); + break; + + case X86_VENDOR_AMD: + amd_model(c); + break; + + case X86_VENDOR_CENTAUR: + centaur_model(c); + break; + } + return; +} + + /* * Perform early boot up checks for a valid TSC. See arch/i386/kernel/time.c */ @@ -1332,9 +1338,7 @@ get_cpu_vendor(&boot_cpu_data); if(boot_cpu_data.x86_vendor != X86_VENDOR_CYRIX) - { return; - } cyrix_model(&boot_cpu_data); } @@ -1374,10 +1378,10 @@ char *p = buffer; int sep_bug; static char *x86_cap_flags[] = { - "fpu", "vme", "de", "pse", "tsc", "msr", "pae", "mce", - "cx8", "apic", "10", "sep", "mtrr", "pge", "mca", "cmov", - "pat", "17", "psn", "19", "20", "21", "22", "mmx", - "24", "kni", "26", "27", "28", "29", "30", "31" + "fpu", "vme", "de", "pse", "tsc", "msr", "pae", "mce", + "cx8", "apic", "10", "sep", "mtrr", "pge", "mca", "cmov", + "pat", "17", "psn", "19", "20", "21", "22", "mmx", + "24", "kni", "26", "27", "28", "29", "30", "31" }; struct cpuinfo_x86 *c = cpu_data; int i, n; @@ -1388,15 +1392,15 @@ continue; #endif p += sprintf(p,"processor\t: %d\n" - "vendor_id\t: %s\n" - "cpu family\t: %c\n" - "model\t\t: %d\n" - "model name\t: %s\n", - n, - c->x86_vendor_id[0] ? c->x86_vendor_id : "unknown", - c->x86 + '0', - c->x86_model, - c->x86_model_id[0] ? c->x86_model_id : "unknown"); + "vendor_id\t: %s\n" + "cpu family\t: %c\n" + "model\t\t: %d\n" + "model name\t: %s\n", + n, + c->x86_vendor_id[0] ? c->x86_vendor_id : "unknown", + c->x86 + '0', + c->x86_model, + c->x86_model_id[0] ? c->x86_model_id : "unknown"); if (c->x86_mask || c->cpuid_level >= 0) p += sprintf(p, "stepping\t: %d\n", c->x86_mask); @@ -1411,38 +1415,35 @@ /* Cache size */ if (c->x86_cache_size >= 0) p += sprintf(p, "cache size\t: %d KB\n", c->x86_cache_size); - + /* Modify the capabilities according to chip type */ switch (c->x86_vendor) { - case X86_VENDOR_CYRIX: - x86_cap_flags[24] = "cxmmx"; - break; + case X86_VENDOR_CYRIX: + x86_cap_flags[24] = "cxmmx"; + break; - case X86_VENDOR_AMD: - if (c->x86 == 5 && c->x86_model == 6) + case X86_VENDOR_AMD: x86_cap_flags[10] = "sep"; - if (c->x86 < 6) x86_cap_flags[16] = "fcmov"; - x86_cap_flags[22] = "mmxext"; - x86_cap_flags[30] = "3dnowext"; - x86_cap_flags[31] = "3dnow"; - break; + x86_cap_flags[22] = "mmxext"; + x86_cap_flags[30] = "3dnowext"; + x86_cap_flags[31] = "3dnow"; + break; - case X86_VENDOR_INTEL: - x86_cap_flags[17] = "pse36"; - x86_cap_flags[18] = "psn"; - x86_cap_flags[24] = "osfxsr"; - break; + case X86_VENDOR_INTEL: + x86_cap_flags[17] = "pse36"; + x86_cap_flags[18] = "psn"; + x86_cap_flags[24] = "osfxsr"; + break; - case X86_VENDOR_CENTAUR: - if (c->x86_model >=8) /* Only Winchip2 and above */ - x86_cap_flags[31] = "3dnow"; - break; + case X86_VENDOR_CENTAUR: + x86_cap_flags[31] = "3dnow"; + break; - default: - /* Unknown CPU manufacturer. Transmeta ? :-) */ - break; + default: + /* Unknown CPU manufacturer. Transmeta ? :-) */ + break; } sep_bug = c->x86_vendor == X86_VENDOR_INTEL && @@ -1453,31 +1454,31 @@ c->x86_mask < 3; p += sprintf(p, "fdiv_bug\t: %s\n" - "hlt_bug\t\t: %s\n" - "sep_bug\t\t: %s\n" - "f00f_bug\t: %s\n" - "coma_bug\t: %s\n" - "fpu\t\t: %s\n" - "fpu_exception\t: %s\n" - "cpuid level\t: %d\n" - "wp\t\t: %s\n" - "flags\t\t:", - c->fdiv_bug ? "yes" : "no", - c->hlt_works_ok ? "no" : "yes", - sep_bug ? "yes" : "no", - c->f00f_bug ? "yes" : "no", - c->coma_bug ? "yes" : "no", - c->hard_math ? "yes" : "no", - (c->hard_math && ignore_irq13) ? "yes" : "no", - c->cpuid_level, - c->wp_works_ok ? "yes" : "no"); + "hlt_bug\t\t: %s\n" + "sep_bug\t\t: %s\n" + "f00f_bug\t: %s\n" + "coma_bug\t: %s\n" + "fpu\t\t: %s\n" + "fpu_exception\t: %s\n" + "cpuid level\t: %d\n" + "wp\t\t: %s\n" + "flags\t\t:", + c->fdiv_bug ? "yes" : "no", + c->hlt_works_ok ? "no" : "yes", + sep_bug ? "yes" : "no", + c->f00f_bug ? "yes" : "no", + c->coma_bug ? "yes" : "no", + c->hard_math ? "yes" : "no", + (c->hard_math && ignore_irq13) ? "yes" : "no", + c->cpuid_level, + c->wp_works_ok ? "yes" : "no"); for ( i = 0 ; i < 32 ; i++ ) if ( c->x86_capability & (1 << i) ) p += sprintf(p, " %s", x86_cap_flags[i]); p += sprintf(p, "\nbogomips\t: %lu.%02lu\n\n", - (c->loops_per_sec+2500)/500000, - ((c->loops_per_sec+2500)/5000) % 100); + (c->loops_per_sec+2500)/500000, + ((c->loops_per_sec+2500)/5000) % 100); } return p - buffer; } | |