Messages in this thread | | | Subject | Re: readX/writeX semantic and ordering | From | Jes Sorensen <> | Date | 13 Dec 1999 11:25:46 +0100 |
| |
>>>>> "Gerard" == Gerard Roudier <groudier@club-internet.fr> writes:
Gerard> It seems that some implementation of this interface only Gerard> enforces a barrier after the IO/MMIO. If I am right, that Gerard> means that if we want, for example, a STORE to memory followed Gerard> by a writeX to be observed in that order by a PCI device, we Gerard> must insert an explicit barrier between the STORE to memory Gerard> and the writeX, for architectures that implements some weak Gerard> ordering. By the way, this is often the case in PCI device Gerard> drivers.
[snip]
Gerard> Can somebody elaborate, especially about readX/writeX Gerard> implementation for PPC. Thanks.
This was discussed some months ago here and the consensus is that readl/writel are supposed to guarantee ordering just as they do on the x86. However on the Alpha they didn't use to and this was only updated somewhere during 2.3.x, 2.2.x has the old behavior. The PPC macros on the other hand does include the ordering.
With the new interface you also have the option of using __raw_writel/__raw_readl to get non ordered, native byte order access to the PCI shared memory. Which allows you to do optimize the access better in case it makes sense for y our device and you know what you are doing.
Jes
- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.rutgers.edu Please read the FAQ at http://www.tux.org/lkml/
| |