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    SubjectRe: spin_unlock optimization(i386)
    Linus Torvalds <> wrote:

    >And THAT is the assymetry: intel can and will re-order
    > write A
    > read B

    I guess that almost all pipelined processors will reorder this (that's
    not a speculative execution issue), because reads are performed early
    in the pipeline and writes at the end. Suppose we have 5 stages
    (fetch-decode-read-exec-write), then the above two instructions will
    first read B and then write A.

    T0 T1 T2 T3 T4 T5
    write A fetch decode read exec write
    read B fetch decode read exec write

    The read happens in T3 and the write in T4. When doing:

    write A
    read A

    the CPU can detect this and internally forward A from stage 4 directly
    to stage 3. But this doesn't work with SMP since one CPU cannot look
    into the pipeline of the other CPU.

    _ x ___ (Peter Steiner)
    / \_/_\_ /,--' Linux User #55148 (
    \_____/ perl -e'while(<>){s/=\n//g;s/=([\dA-F]{2})/chr(hex($1))/eg;print;}'

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      Last update: 2005-03-22 13:55    [W:0.024 / U:14.540 seconds]
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