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SubjectRe: Are SMP spinlocks safe in WB cached mem?
Robert Redelmeier wrote:
>
> Mikulas Patocka wrote:
> >
> > > Having an SMP box, and noting all the SMP crash reports I did some
> > > light reading :) of the IA32 System Programming Manual. I came
> > > up with a scenario for P6 SMP spinlock corruption/theft:
> > >
> > > CPU0 has and clears spinlock SL. The write is still in cache not mem
> > > CPU1 tries to read SL.
> > > CPU0 sees the read and helpfully signals HITM# and passes the line.
> > > CPU1 starts receiving the line and sets SL
> > > CPU0 "simultaneously" sets SL in it's cache line.
> >
> > When CPU0 starts passing cache line to CPU1, it sets it to SHARED state,
> > which prevents any atomic writes to it. If not, it's bug in CPU.
>
> But the IA32 SysPgmMan (Table 9.2 IIRC) says a write to a MESI shared
> line merely is forced to memory (which the other CPU is expected to
> snoop).

Sorry, that was Table 9.3 and:
Table 9-3 MESI Cache Line States a write to a Shared line
…causes the processor to gain exclusive ownership of the line

Very nice. But what about "simultaneous" writes?

> AFAIK, all aligned writes are atomic. Now the question is, how does
> LOCK affect MESI ? It ought to force an "invalid", but may not for
> performance reasons.

-- Robert

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