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SubjectRe: serial.c (race?)
From
   Date:   Sat, 16 Oct 1999 09:18:38 +0200 (MEST)
From: R.E.Wolff@BitWizard.nl (Rogier Wolff)

The transmit routine is kind of brain-dead. It waits for the FIFO to
drain completely, and then shoves complete FIFO depth of data into the
transmitter. This means that when the system has an IRQ latency larger
than a byte transmit time, (I.e. when you actually need the input
FIFO), then you will generate gaps in the output stream.

All UART's don't have a way of determining how much space is in the FIFO
(except when it's empty), and most UART's don't have a way of sending an
interrupt except when the FIFO completely drained. Some newer UART's,
such as the 16650, do have a way of sending an interrupt before the FIFO
is completely drained, but I haven't wanted to make the interrupt
service routine far more complicated to support the various different
UART's, especially since it would mean adding a number of extra branches
and I/O port reads (which would be a disaster over the 8MHz ISA bus ---
the ISA bus must DIE!).

Furthermore, unless you have some really brain-damaged drivers in your
system, in practice it's really not an issue anyway. (If you really
care about performance for some real-time data acquisition system, for
example, what the heck are you doing with a non-DMA IDE controller? :-)

- Ted

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