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SubjectRe: ECP+EPP mode problem with IOMEGA Zip
Date sent:      	Thu, 21 Jan 1999 19:11:34 +0100
From: Jan Kara <jack@atrey.karlin.mff.cuni.cz>
To: Tim Waugh <tim@cyberelk.demon.co.uk>
Copies to: linux-kernel@vger.rutgers.edu, David Campbell <campbell@torque.net>
Subject: Re: ECP+EPP mode problem with IOMEGA Zip

> Hello.
>
> > Could you show me the output from id_probe (the diagnostic utility)? That
> > would be handy.
> >
> > Tim.
>

*snip*

> Here I'm also sending you an output of id_probe:
>
> Probing port 03bc
> Probing port 0278
> Probing port 0378
> SPP port present
> ECP with a 16 byte FIFO present
> PS/2 bidirectional port present
> Failed Intel bug check. (Phony EPP in ECP)

The "Intel bug check" refers to the EPP timeout bit (bit 0 of the parallel port
status register [parallel port base + 1 = 0x379]) is always stuck low. EPP is
something that is extremely difficult to detect and the state of the EPP
timeout bit becomes critical during probes.

Where EPP becomes tricky is that while accessing the EPP data ports (base+4 to
base+7) the CPU is held in a HALT state until the EPP transaction is complete.
If there is no EPP device present then after a small period (10 usec normally)
the IO chipset releases the CPU and sets the EPP timeout bit high.

A small number of IO chipsets do not have the EPP timeout function hence if
there is no EPP device then the CPU is permantly in the HALT state and nothing
happens LITERALLY! <CNTL><ALT><DEL> does not even function! The bulk (if not
all) the IO chipsets in this category fail the bug check test, as a result it
is assumed there is no EPP (or to dangerous to use). This may prevent some
valid chipsets working properly.

If you have a desktop machine that you can open the case, you could help me by
locating the IO chipset and send me the details. I will need to know the
manufactuer and part number. The manufacturers I know about are SMC, National
Semiconductor and Win Bond (these companies make pdf technical spec files
publicly available). From this information it is possible to locate the
configuration registers that the mainboard BIOS uses to read the parallel port
state. It is a lot cleaner and safer than performing the "black magic" that is
currently used.

David Campbell

"All parallel ports are equal, some are more equal than others"
=======================================================
campbell@torque.net
Check http://www.torque.net/parport for all Linux parallel port solutions.
Current project list:
a) Get ZIP Plus drive back from waranty claim
b) Maintain Linux ZIP drivers (need to update docs)

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