Messages in this thread | | | Date | Tue, 8 Sep 1998 15:20:15 +0100 | From | Jamie Lokier <> | Subject | Re: IPv4 kernel messages |
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On Mon, Sep 07, 1998 at 10:33:05PM +0200, MOLNAR Ingo wrote: > yep it was developed on a PII, which has a pipelined MMX unit. Also make > sure both buffers are 8 byte aligned. (which is usually not true for > random malloc() or auto-allocated buffers). wrong alignment causes very > bad MMX performance.
I believe the P5 MMX unit is also somewhat pipelined. 8 byte alignment is very important, but perhaps equally important (according to an MMX conference I attended a couple of years ago) is the order in which you read and write within cache lines.
Because the P5 does write-through caching while PII does write-back, I'd expect the read and write ordering to be a lot more critical for the P5.
This means you have to be (1) cache aligned, not just 8 bytes; (2) have to get the access order right, don't ask me what it is though :-)
Really, the right MMX checksum on the P5 should max out the memory busses. The overhead would be in the FPU context save/restore and switching to MMX mode.
-- Jamie
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