Messages in this thread | | | Date | Sun, 20 Sep 1998 21:16:32 -0500 (CDT) | From | "Andre M. Hedrick" <> | Subject | Re: EPOX and VIA |
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On Sun, 20 Sep 1998, Kurt Garloff wrote:
> On Fri, Sep 18, 1998 at 03:43:48PM -0500, Andre M. Hedrick wrote: > > This should be correctly supported as of 2.1.122 with the addition if > > via82c586.c code for setting chipset timing controls. You must > > enable this in the configure process. This is considered EXPERIMENTAL > > do to all of the earlier VIA chipset through the present use the same > > ID codes for the IDE controller. This directly implies that earlier > > that VP3 and MVP3 boards may not except these settings. The bigger task > > related to this chipset is to pre-detect the revision and provide > > work-arounds as avaliable. > > Cause you asked: > My Apollo-VP (FIC PA-2010) likes the via82c586.c code. I had IDE DMA > problems before and they're gone since 2.1.122. It's not UDMA, however. > Bus 0, device 7, function 1: > IDE interface: VIA Technologies VT 82C586 Apollo IDE (rev 2). > Medium devsel. Fast back-to-back capable. Master Capable. Latency=32. > I/O at 0x6000 [0x6001]. > Non-prefetchable 32 bit memory at 0xe0804000 [0xe0804000]. > > <4>VP_IDE: IDE controller on PCI bus 00 dev 39 > <4>VP_IDE: not 100ative mode: will probe irqs later > <4> ide0: BM-DMA at 0x6000-0x6007, BIOS settings: hda:pio, hdb:pio > <4>ide0: VIA Bus-Master (U)DMA Timing Config Success > <4>hda: SAMSUNG WN321620A (2.16 GB), ATA DISK drive > <4>ide0 at 0x1f0-0x1f7,0x3f6 on irq 14 > <6>hda: SAMSUNG WN321620A (2.16 GB), 2060MB w/109kB Cache, CHS=523/128/63, DMA > > The problems started when I changed from 6x86-P200 (150MHz) to K6-2-300 > (running at 3.5 x 83.3 or 4 x 75 MHz). The BIOS doesn't detect the CPU > correctly nor the speed. I guess it doesn't initialize the IDE chips with > the correct timings, so the via82c586 is really helpful to me. Thanks, Andre!
Thanks goes to Michel Aubry <giovanni@sudfr.com> the person I rely on for VIA code fixes. I have done a lot of work on the drivers myself, but I really hope to manage and contribute as able.
> (And, yes, I patched the kernel to enable Write Allocation for my K6.) > > > BTW: Will anyone correct this log message to be not ,,100% native mode``? I > remember this was discussed before and the sources look fine to me, so it > might be printk's fault or the one of klogd/syslogd. > > ide-pci.c:330: printk("%s: not 100%% native mode: will probe irqs later\n", d->name); > ide-pci.c:340: printk("%s: 100%% native mode on irq %s\n", > ide-pci.c:343: printk("%s: 100%% native mode on irq %d\n", d->name, pciirq);
IMHO, this needs to stay. Here is a case where it reports correctly
AEC6210: IDE controller on PCI bus 00 dev a0 AEC6210: not 100% native mode: will probe irqs later AEC6210: ROM enabled at 0xfebf8000 AutoDMA enabled ide0: BM-DMA at 0xef90-0xef97, BIOS settings: hda:pio, hdb:pio ide1: BM-DMA at 0xef98-0xef9f, BIOS settings: hdc:pio, hdd:pio PDC20246: IDE controller on PCI bus 00 dev 98 PDC20246: 100% native mode on irq 18 ide2: BM-DMA at 0xef40-0xef47, BIOS settings: hde:DMA, hdf:DMA ide3: BM-DMA at 0xef48-0xef4f, BIOS settings: hdg:DMA, hdh:DMA
The Promise Technology IDE UltraDMA/33 will do native and non-native reporting. Since there are older and (newer) different ide-controllers, it is functional code and is valid. The above case should be the proof in the pudding.........
Note that ACARD's AEC6210 is a modified ATP850UF SCSI chipset to handle IDE-devices with the power of SCSI. Interrupts below are in HEX and SMP ioapic reported and shifted.
PCI devices found: Bus 0, device 20, function 0: SCSI storage controller: Artop Electronics ATP850UF (rev 1). Fast devsel. IRQ 13. Master Capable. Latency=254. I/O at 0xeff0 [0xeff1]. I/O at 0xefe4 [0xefe5]. I/O at 0xefa8 [0xefa9]. I/O at 0xefe0 [0xefe1]. I/O at 0xef90 [0xef91]. Bus 0, device 19, function 0: IDE interface: Promise Technology IDE UltraDMA/33 (rev 1). Medium devsel. IRQ 12. Master Capable. Latency=64. I/O at 0xefa0 [0xefa1]. I/O at 0xef8c [0xef8d]. I/O at 0xef80 [0xef81]. I/O at 0xef88 [0xef89]. I/O at 0xef40 [0xef41].
Cheers, Andre Hedrick
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