Messages in this thread | | | From | Andrew Derrick Balsa <> | Subject | Cyrix CPUs, 2.0.35-pre6 and 2.1.115 and later kernels | Date | Sat, 22 Aug 1998 11:25:35 +0200 |
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Hi,
2.0.35-pre6 is still missing some lines of code from Jumbo-9, that are needed for adequate Cyrix CPU detection.
Here is what I get on a Cyrix MII, with 2.0.35 + Jumbo-9:
processor : 0 cpu : 686 model : M II @ 233.86MHz +/- 0.01MHz vendor_id : CyrixInstead stepping : 2.8, core/bus clock ratio: 3.5x fdiv_bug : no hlt_bug : no f00f_bug : no fpu : yes fpu_exception : yes cpuid : yes wp : yes flags : fpu de tsc msr cx8 pge cmov mmx bogomips : 233.47
I think it's clear enough that 2.8 is the stepping, and 3.5x is the core/bus clock ratio.
Similarly, one gets improved CPU detection for the AMD K6 CPUs, and late Intel CPUs (but without the core/bus clock ratio detection, since this is only available on Cyrix CPUs).
As for 2.1.115+: Rafael Reilova maintains this code, but he is away for 3 weeks on vacations. Please report any problems to his email: <rreilova@ececs.uc.edu> and he will fix/patch the detection code as needed ASAP.
Oh, and about the random CPU lockups: as mentionned by Alan Cox, we don't have a kernel patch to solve that kind of problem. :-) There are many good sites on the Web that discuss these hardware problems: Tom's Hardware Site, Anandtech, Tweakit, etc...
Cheers, -- Andrew D. Balsa andrebalsa@altern.org
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