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    SubjectRe: Notebooks
       Date: 	Wed, 19 Aug 1998 07:51:08 +0200
    From: Andi Kleen <ak@muc.de>

    My theory is that it is caused by better cache line usage.

    No theory necessary Andi, I actually measured it with the UltraSPARC
    cache hit/miss counters when you made those changes :-)

    Later,
    David S. Miller
    davem@dm.cobaltmicro.com

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