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SubjectRe: patch to trim page table cache
   Date: 	Sat, 18 Jul 1998 11:29:10 -0400
From: Bill Hawes <whawes@star.net>

Revised patch sans locking changes is attached. One remaining
question is whether the kswapd process can migrate between CPUs in
an SMP system. If not, I'll need to find some way to drain the
other CPU caches.

And for this reason I think these cache trimming patches are dubious:

1) On a uniprocessor the memory consumption of the pte caches are
not even on the radar.

2) On an SMP system, you can only immediately trim the local cpu's
pte cache.

Then what is the use?

Note, I kept the cache trimming in the idler loop specifically because
when the machine begins to get memory pressure (to the point where we
would actually begin to care about pte cache consumption) there is
always a quick thread of control into the idler task for at least one
iteration while people block. I tested this, and this is why I am so
against your cache trimming changes. Please show me evidence that the
current heuristics are insufficient and do not work, I put a lot of
time into it's design.

Your misunderstanding of the per-cpu locking issues evidences that you
did not study it's inner workings and heuristics very well, so as a
result I'm quite leery of the changes you are making.

Later,
David S. Miller
davem@dm.cobaltmicro.com

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