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SubjectRe: uniform input device packets?
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but what about multiple events? (move the mouse diagnally while clicking a
button) 3 2/4 byte reads+mangle could be combined to 1 cache read while 3 16
byte reads would be 3 cache reads.

David Lang


On Fri, 26 Jun 1998, Mike Jagdis wrote:

> Date: Fri, 26 Jun 1998 12:13:34 +0100 (GMT/BST)
> From: Mike Jagdis <mike@roan.co.uk>
> To: Allanah Myles <dossy@panoptic.com>
> Cc: linux-kernel@vger.rutgers.edu
> Subject: Re: uniform input device packets?
>
> On Fri, 26 Jun 1998, Allanah Myles wrote:
>
> > I'd rather read 2 bytes and mangle their bits around rather than
> > having to, say, read 16 bytes to obtain the same amount of data.
> > Unless, you can tell me that it's faster to just read the 16
> > bytes.
>
> Well, lets think about it for a minute... Cache loads happen
> in terms of groups of bytes so reading a few more bytes is
> not very low cost. Write gathering and write back means
> that writing a few more bytes is also low cost. Instructions
> to move data to and from memory can typically execute in
> parallel on pipelined processors so moving a few more bytes
> is also low cost again.
>
> Now on the 6x86 at least bit shift operations are only
> performed in the X pipeline, cause a pipeline stall, and
> are relatively slow compared to memory loads and stores.
> You can do a lot of memory loads and stores in the time
> it takes to do a bit shift.
>
> I think you might find that a 16 byte read is actually
> faster than a 2 byte read and mangle...
>
> Mike
>
> --
> .----------------------------------------------------------------------.
> | Mike Jagdis | Internet: mailto:mike@roan.co.uk |
> | Roan Technology Ltd. | |
> | 54A Peach Street, Wokingham | Telephone: +44 118 989 0403 |
> | RG40 1XG, ENGLAND | Fax: +44 118 989 1195 |
> `----------------------------------------------------------------------'
>
>
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>

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