Messages in this thread | | | Date | Sun, 21 Jun 1998 05:29:25 +0200 (MET DST) | From | MOLNAR Ingo <> | Subject | Re: Thread implementations... |
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On Sat, 20 Jun 1998, David S. Miller wrote:
> I assumed that TSS switches were defined to reload csr3, which by > definition flushes the TLB of user entires. > > Thats broken, not because it's a silly workaround for the Intel TLB > mis-design, but rather because it changes behavior from what older > CPU's did. So if someone optimized things to defer TLB flushes for > mapping changes, when they knew they would task switch once before > running the task again, this "microcode optimization" would break the > behavior such a trick would depend upon.
unless this deferred TLB flush feature gets into 2.1, i plan on making a new version of the softswitch stuff (that replaces TSS switching) for 2.3, which should give us more pronounced control over TLB flushes and more ...
-- mingo
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