Messages in this thread | | | Date | Thu, 18 Jun 1998 21:34:12 -0700 | From | "David S. Miller" <> | Subject | Re: f@#$ing MMX emulator |
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Date: Fri, 19 Jun 1998 16:22:24 +1200 From: Chris Wedgwood <chris@cybernet.co.nz>
> You seem to allude later that MMX should have used another bank of > registers, Sparc VIS does not do this and uses the normal FPU. I > don't know if you were driving at things being different here between > Sparc and Intel, but in any event they aren't in this regard.
How long does it take for the sparc to save/restore all the FPU registers?
Depends, the 64-bit sparc keeps track at all times whether the top 32 and bottom 32 fpu registers have been dirtied or not. But for worst case, it's 4 block store instructions to save the entire register file. Considering store buffer and L2 cache write latencies, it can work out to somewhere between 32 and 48 cycles, again this is worst case.
We pull a lot of tricks to delay the fpu saves as much as possible. For example, most of the time we can do a full VIS block copy operation, and never save any fpu state due to it. This is primarily what justifies us to use VIS so extensively in the sparc64 kernel.
Later, David S. Miller davem@dm.cobaltmicro.com
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