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SubjectRe: Cyrix 6x86MX and Centaur C6 CPUs in 2.1.102
Hello Vojtech,

Vojtech Pavlik wrote:
>
> On Thu, May 21, 1998 at 05:33:10PM -0100, André Derrick Balsa wrote:
>
> > > Yes, but for all the chips produced up to now it is equal, and for later
> > > chips we may decide based on the chip revision / manufacturer and if needed
> > > apply a TSC per sec / CPU clocks per sec ratio for the respective chip to
> > > get the correct CPU frequency.
> >
> > Well, in fact the TSC *is* supposed to *exactly* count CPU clock cycles,
> > so I don't see what Martin means by "CPU clock speed need not be equal
> > to TSC frequency".
> >
> > Please enlighten me :)
>
> AFAIK the fact that TSC is the count of CPU cycles is not guaranteed
> anywhere - there is no specifocation or databook or anything saying it. It
> is guaranteed to advance forward at some constant speed, and not to give the
> same the same value in 2^x years. That's all. No mention of CPU speed.

Hmmm, perhaps the following will help:

From IBM Application Note 40250:

"The Time Stamp Counter (TSC) Register (MSR10) is a 64-bit counter that
counts the internal CPU clock cycles since the last reset."

The Cyrix 6x86MX Data Book uses exactly the same phrase.

The IDT C6 Data Sheet says:
"Both the IDT Winchip C6 processor and the Pentium processor have a
64-bit MSR that materializes the Time Stamp Counter (TSC). Both systems
increment the TSC once per processor clock."

The Intel Application Note RDTSCPM1.PDF "Using the RDTSC Instruction for
Performance Monitoring" says:

"The Time Stamp Counter keeps an accurate count of every cycle that
occurs on the processor. The Intel Time Stamp Counter is a 64-bit MSR
(Model Specific Register) that is incremented every clock cycle."

I didn't check the AMD K6 Data Book but I assume it says something
similar.

So, it seems the TSC is a CPU clock cycle counter after all. It is _not_
guaranteed to advance at a constant speed, however it _is_ guaranteed to
advance at the same speed as the processor. :)

Of course, being a 64-bit counter means that if left alone counting, it
will take some time to repeat the same value... ;)

Regards,
------------------------
André Balsa
andrebalsa@altern.org
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