Messages in this thread | | | From | (Alan Cox) | Subject | Re: GGI, EGCS/PGCC, Kernel source | Date | Wed, 25 Feb 1998 19:23:06 +0000 (GMT) |
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> protocol, it gets thousands of calls per second. The accelerator of most > cards is a different beast though. It usually has a limited queue depth > (8, 16, 32), where a command can take up 1-5 queue entries. So certain
Yes but you dont have to go back to user space each time you fill the hardware queue.
> possibly millions of accelerated operations per second. Smallish > accelerated operations finish within 10-100 cycles, this is why almost no > GX card has IRQ-driven acceleration, they have an engine status/depth > register that can be polled. If you let users access the framebuffer as > well then 'delayed syncing' (a technique in XFree86 XAA that has almost > doubled acceleration performance ...) can not be done safely.
Now that depends on two things
1. If you only allow one user to have the frame buffer a time and keep context on switches.
2. If you dont pull MMU stunts to fault/block other tasks touching the memory during such events. Also note most operations take so few cycles a non scheduling spin is no big deal (SMP needs the mmu stunt always alas).
Alan
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