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SubjectRe: CAUGHT IN THE ACT: evidence of clock skew on Intel SMP
On Fri, 4 Dec 1998, Colin Plumb wrote:

>Thanks to everyone who has been sending me SMP skew-testing results.
>I have some cleaner V2 code below which tries to reduce some sources
>of skew in the code by forcing both master and slave to use the
>same message-seding code, but I have found a smoking gun in a
>dual PPro 180 MHz that someone sent me the results from:

After fixing the code a bit (moving receive_ready up, fixing NAMPLES ->
NSAMPLES), I get nothing really interesting on a Tyan Tomcat IV with 2x
Pentium 233MMX:

59 56
52 56
56 56
56 56
56 56
56 56
56 56
56 56
56 56
56 56
56 56
56 56
56 56
56 56
56 56
56 56
56 56
56 56
56 56
56 56
56 56
56 56
56 56
56 56
56 56
V2: min1 = 52, min2 = 56, diff = -4

-George


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