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SubjectRe: 2.2.0pre1 OOPS on boot.
Date
> it's needed in latest kernels for the timer interrupt. Note that earlier

Its only needed because someone took out the rather sensible code that meant
it wasnt needed (for uniprocessor anyway)

> the existence of the TSC. We had lots of (maintainance) problems due to
> that complexity. The scheduling bits are SMP specific for now, because the
> cost of getting cache issues wrong is magnified on SMP ... but if you look
> at them, the concept is more or less generic and can be applied to UP too.

The SMP ones its obvious why they are needed. For 2.3.x this can be sorted with
linker and segment tricks properly.

> splittered even more these days. I dont think we have a choice, x86 CPUs
> _are_ getting more and more different, there is no reason to pretend
> otherwise.

The more different they get the more they need to be fixed to be one kernel
tree. As it stands now the 2.1.x tree with the right instruciton options
except for tsc for builds doesnt boot on the earlier cyrix chips, the amd k5,
and the cyrix mediagx.

In my tree the timer interrupt is still a jump vector, I can't measure any
performnace difference between that and the older system. It also needs to
know about chips with a tsc that has 'issues'.

The Alpha has been through this pain to the point that people gave up on
the Linux instructions and installed NT simply because they couldn't work out
which kernel to install. We now have a generic kernel for the Alpha, thanks
to deep magic we have a generic kernel for the Sparc - which makes the intel
like look positively sane

The x86 shouldnt make the same mistakes as the Alpha did.

We only have a few differences to address in the near time scale, excepting
the 386.

FPU <-> no FPU
RDTSC <-> mb timer
FXSAVE <-> FSAVE

FXSAVE is figured, RDTSC _was_ sorted, FPU has long been sorted.

Alan


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