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SubjectRE: K6-2CTX MTRR's...

--------Some else wrote :
I set this up with an Elsa VICTORY II (Banshee, AGP, 16 MB SGRAM) and
got nearly 2.5 times for 2D graphics operation and a huge bus transfer
speedup!!! It offers the same as the Pentium II does.

K6,K6/2,K6/2cxt-Utility, Andreas Stiller, c't V 1.1, Nov 98
Syntax: SetK6 /on .. set WA for all memory (found: 128
MByte)
Syntax: SetK6 .. w/o parameter:displays actual configuration
/on:Memorysize .. enable write allocation for memory [in
MByte]
/off .. disable write allocation
SetK6 /M0:LFB,Size[,attr] Write combining for primary LFB
SetK6 /M1:LFB2,Size[,attr] Write combining for second. LFB

CPUID : Typ=00 Fam=05 Mod=08 Step=0C
Processor Name : AMD K6-2CXT Step 12, 401 MHz
PCI Framebuffers : 1. E8000000, 2. EC000000
------
ironic that this would come out earlier today before i posted my question
<g>, because i only get the digest and didn't know someone had asked..
Yes, here are all the processors that now support "MTRR's", i did a little
digging, and...:

Pentium II/Pro : 8? MTRR registers
AMD K6-2CTX/K6-3 : 2 MTRR registers
Cyrix 6x86MX/M2 : 8 ARR (Address Range Registers)
Centaur/IDT Winchip : 8 MCR (Memory Control Registers)

Richard Gooch wrote and maintains the official P2/PPro MTRR code in the
kernel...i've written him because once i write working code for the
Winchip, i'll gladly expand his interface to transparently cover all 4
chips..the problem being that i won't havea K6-2 and a cyrix to test them
out on...i've downloaded all the spec sheets for all 3 processors, so w'll
have to see...

the important thing is getting it to merge with the existing MTRR
interface, so that there's a consistant interface to access all four.
i don't see this making it into official 2.2 thouygh...maybe an unofficial
patch though, or modules...

comments? corrections?
john.c

/* John Clemens http://www.rpi.edu/~clemej _/ */
/* RPI CompE 2000 clemej@rpi.edu _/ Speak Softly, */


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