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    SubjectSecond Thought (Re: Re[2]: Small error?? in IDE dma processing?)

    First lets run some system crashes...........(which I did)....even worse!!

    Then look at the ATA/ATAPI-4 spec T13-1153D Revision 17 30-Oct-97 page 234,
    again. The flow charts on DMA procedure to my reading again (not late at
    night in a dimly lit room at 1am).
    Both branches of the test 0IEN=0 :

    At test DEVICE: nIEN=0 ?

    No -> Host : Read of Status register is recommended.
    NOTE : Status register is read to clear pending interrupt.

    Yes -> Device : Assert INTRQ
    Host : Read Status register
    Device : Negate INTRQ

    wait for device to issue interrupt request
    then first read the status ***
    then clear the interrupt

    It is not all clear if this is refering to DMA or Drive Status; however,
    it is reasonable to assume that it is DMA first.

    Like the original code.

    A closer look at 29055002.pdf (intel), 29765804.pdf (intel),
    d1153r17.pdf, and some source code on loan from HighPoint Tech.
    (a public branch of Triton).

    I now think the original code is correct.
    Note that I will test this question more objectively on a drive that
    doesn't have some non-correctable error accounting.
    (forgot to bad block check and mark the drive first, duh....)

    Have you switched the code and tested it youself yet?

    On Wed, 16 Dec 1998 wrote:

    > Will you make the appropriate changes to 2.0 and 2.1 IDE code?

    If this is the correct solution, yes. I am now not convinced that it is
    the correct answer. The follow up docs on the PIIX/PIIX3 have a DMA
    BusMaster bit order corrections, also.

    Andre Hedrick
    The IDE-FNG for Linux
    The APC UPS Specialist for Linux

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