Messages in this thread | | | Date | Wed, 25 Nov 1998 08:38:37 +0100 (MET) | From | Gabriel Paubert <> | Subject | Re: Non-page-aligned PCI base address |
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On Tue, 24 Nov 1998, Martin Mares wrote:
> Hi, > > > Does anybody has an idea how to fix above ? I couldn't find anything about > > it in any docs/code. The box where my kernel module was tested (AMI > > Motherboard Goliath II PCI/EISA) has 7 PCI slots on 2 buses (that means, > > probably too much), and by some cards I got > > > > this strange base 0 addr: 0xfebffd80 (as found in pci_dev->base_address[0]; > > ^^^ > > The size of base0 is 0x80. Is it possible that bios makes some attempts > > to 'save' address space, being too pedantic ? > > > > This is bad if I want to perform ioremap() to access control registers of > > the card through mapped memory (needed in ISR for IRQ status/config regs > > access). The kernel where it was tested was 2.1.108. Momentary, I'm > > aligning the address to the nearest bottom page and ioremap it, keeping > > track of the address offset when accessing it. But is sucha thing realy > > necessary ? > > > > Please cc my address if you got some answer, as I'm not subscribed here. > > This seems to be perfectly correct -- PCI just states every memory / I/O > region has to be aligned to a multiple of its size and that the size is > a power of two >= 16 (memory) or 4 (I/O). Therefore you cannot expect > memory regions smaller than 4K to be page-aligned. > > Anyway, can you send me lspci -vvx output for this device? >
Yeah, but ioremap() on x86 fails when the physical address you request to remap is not page-aligned. It doesn't on Sparc/Alpha and PPC AFAICT from a cursory reading of the code since all the PCI memory space is mapped.
I consider this as both a bug and a feature :-):
- the bug: PCI spcifications dor not require it, - the feature: if you use mmap to PCI space from user mode like X does, it is better to have at most one device per page, and in this case the device area can always be page aligned.
Gabriel.
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