Messages in this thread | | | Date | Tue, 17 Nov 1998 10:58:57 -0500 | From | Tony Caola <> | Subject | Problem 450GX chipset NOT PCI 2.1? |
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Despite detection and documentation indicating the contrary: (From linux 2.1.125 bootup: PCI: PCI BIOS revision 2.10 entry at 0xfd091)
It appears that from the attached technical note from Intel's website that the 450GX chipset is NOT 2.1 compliant.
Intel support: This appears to be causing a problem with the hardware we intend to use -- is there a fix or upgrade path available to us? The machines we have are AP450GX's with C0 stepping.
Linux kernel list: Do the 2.1.X kernels have any 'correction' for this built-in? I have a suspicion that this is causing incompatibility between the drivers for PacketEngines's GNIC I (yellowfin) and GNIC II (hamachi) cards and these motherboards. Have any other problems with this chipset been reported under Linux? I think the GX chipset supports the new Xeon processors, so this may become an even bigger headache. Please copy me when responding to the list -- I am not yet subscribed.
Thanks!
Anthony Caola Massachusetts Institute of Technology Phone: (617) 253-6547 Department of Chemical Engineering 25 Ames St., Building 66-250 Email: caola@bigfoot.com Cambridge, MA 02139
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(http://support.intel.com/support/chipsets/450gx/KB49QMA7.HTM) Title: PCI RETRY Cycles with the 450GX Chipset
Product: 450GX
Stepping: All
Abstract: This document discusses that the 450GX was designed to meet PCI 2.0 specification and does not support the PCI 2.1 requirement of issuing a RETRY if a target cannot complete the initial data phase of a transaction in 16 or 32 PCI clocks.
Problem: The current PCI specification, 2.1, requires that if a target cannot complete the first data phase of a transaction within 16 PCI clocks, it must issue a RETRY to the master. The master is then required to repeat the exact same request at a later time. Also, if the target is a PCI->host bridge that is snooping, it may exceed the 16 clock rule, but may never exceed 32 PCI clocks before issuing a RETRY. In some cases, the 450GX has been found to violate this specification and take longer than the 16 or 32 PCI clocks allowed without issuing a RETRY and not completing the first data phase of the requested transaction.
Solution: The 16/32 PCI clock rule is new to the PCI 2.1 specification(section 3.5.1.1). This rule was added to prevent situations in which a PCI target will hold off a transaction indefinitely if it cannot access or provide the requested data for the current transaction. The 450GX was designed to meet the PCI 2.0 specification and does not support the 16/32 PCI clock rule. Therefore, the 450GX may take longer than 16 or 32 PCI clocks to complete the first phase of a PCI request.
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