Messages in this thread | | | Date | Thu, 5 Jun 1997 11:43:49 +0200 (MET DST) | From | Ingo Molnar <> | Subject | Re: pre2.0.31-2 |
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On Wed, 4 Jun 1997, Leonard N. Zubkoff wrote:
> From: alan@lxorguk.ukuu.org.uk (Alan Cox) > Date: Wed, 4 Jun 1997 20:30:21 +0100 (BST) > > > 1) The memory mapped by 'vremap' is marked cacheable. This > > is (almost certainly) incorrect as it is memory that is > > actually device memory. Note that the mmap call used by > > X servers marks the memory as uncached. > > The PC architecture is supposed to handle this for you. It could well > be an issue on MIPS and friends. The X one is hack and shouldnt be needed > > Indeed, I recall reading somewhere in the 440FX Natoma (or 430HX) chipset > documentation that there was no caching on any PCI memory accesses.
last i recall the mechanizm is two-sided, once there are possible MTTR settings for a memory area, second there is the caching bit in the page table entry. The CPU uses the worst setting.
so if you have a BIOS that say sets some more clever MTTR value for certain memory ranges, it might make a difference wether you set the page table entry caching or nocaching. [there was one report that ioremap_nocache() on 2.1 made difference on a high end device driver.]
-- mingo
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