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SubjectRe: linux-2.1.42 question
   From: (Alan Cox)
Date: Fri, 20 Jun 1997 23:15:22 +0100 (BST)

Swap it for nops and see what occurs. This is however exactly the
kind of spot you find tlb/pipeline bugs in a lot of CPU's.

On the HyperSparc I cannot execute a "tlb flush all" instruction in a
branch delay slot, it can watchdog reset the cpu if the branch
destination sits at the begining of a cache line and the pipe stalls
due to the cache line cross... poof

UltraSparc is much nicer, and faster too 8-)

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