lkml.org 
[lkml]   [1997]   [Jun]   [20]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
/
Date
From
SubjectRe: linux-2.1.42 question
   From: alan@lxorguk.ukuu.org.uk (Alan Cox)
Date: Fri, 20 Jun 1997 23:15:22 +0100 (BST)

Swap it for nops and see what occurs. This is however exactly the
kind of spot you find tlb/pipeline bugs in a lot of CPU's.

On the HyperSparc I cannot execute a "tlb flush all" instruction in a
branch delay slot, it can watchdog reset the cpu if the branch
destination sits at the begining of a cache line and the pipe stalls
due to the cache line cross... poof

UltraSparc is much nicer, and faster too 8-)


\
 
 \ /
  Last update: 2005-03-22 13:39    [W:0.063 / U:0.084 seconds]
©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site