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SubjectRe: ISA bus and SLOW_DOWN_IO
Date

"Richard B. Johnson" <root@analogic.com> writes:
>Now, using the "old fashoned" pause method of:
>
> jmp foo
> foo:
>
>Is not too effective because with high-speed CPUs and built-in caches,
>you will not waste enough time. However, accessing RAM is predictable
>because PC class RAM access times will not get much faster than 60 ns.
>
>I suggest that the macro be changed to:
>
> pusha
> popa
>
>This will access the stack with a known number of processor clocks plus
>read/write access time. These accesses are not on the ISA bus.

Ok, I follow everything up to this point, and it all makes perfect
sense to me, but wont the above delay with memory accesses usually
end up in the L1 cache or L2 cache? In which case we're back to the
clock speed of the processor, or at least near to it.

I suggest that this is a place where we need to make
use of our carefully calculated BOGOMIPS number. If someone can look up
exactly how long a delay we want here, we can calabrate a loop that
takes the right amount of time.

--
Eric Schenk www: http://www.dna.lth.se/~erics
Dept. of Comp. Sci., Lund University email: Eric.Schenk@dna.lth.se
Box 118, S-221 00 LUND, Sweden fax: +46-46 13 10 21 ph: +46-46 222 96 38

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