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SubjectRe: MMX Technologie

On Sun, 23 Mar 1997, Keith Rohrer wrote:

> Dunno about AMD cache sizes.

Have a look at and
follow the arrows. The main features are:

Cache are 32kB each (I and D), but only 2-way set associative.
Instruction fetcher performs predecoding and stores the additional
information along with the instructions in I-cache.

Floating point multiply takes only 2 cycles (5 on PPro).

Floating point add takes 2 cycles (3 on PPro).

Much lower branch misprediction penalty than PPro.

Fits into a Pentium socket.

But I don't have any to check their claims. Anyway it looks good even after
removing marketing hype.


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