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SubjectRe: Triton DMA
Gerard Roudier wrote:
> On Sat, 29 Nov 1997, Rogier Wolff wrote:
> >
> > In the beginning, parity was considered reasonable: Measurements
> > showed that say only one in a million bits went wrong. In that
> > situation, using parity is not that bad: there is just a 1 chance in a
> > million that a second bit error occurs in that same byte. You
> > possibly miss just one error in a million, 999,999 are flagged
> > correctly. This means that 1 in 1.25e11 bytes is incorrectly flagged
> > as correct while in reality it is wrong.
> >
> > However nowadays we know, that it doesn't always work like that. You
> > might have a 1 in four million chance of a BYTE going wrong, with an
> > average of 4 bits wrong in that byte (i.e. the byte is completely
> > random). Still just one bit in a million is wrong, but a completely
> > random byte has a 50/50 chance of getting the right parity by
> > accident. So now you're getting 1 byte in 1e6 bytes flagged
> > as correct while in reality it is wrong.
> >
> > In the first case, you get one error per day of full-time copying. In
> > the second case you get 5 errors per second. (Assuming 5Mb per
> > second).

> Thanks for the explanation.
> Btw, I did not observe that my Ultra Wide SCSI BUS ever got 40
> undetected errors per second. But I read that IDE DMA may corrupt
> data and noticed that PIO is often recommended against DMA.

Stop! I just took a "one bit in a million" as an example. The real
rate may be 1000 or 1000000 less often, leading to error rates that
are a little more beleivable.

Incorrectly terminated SCSI busses or too long a SCSI bus lead to
erratic behaviour. Same (cable too long, or improper termination)
goes for IDE. (From the 16Mb/sec mode upwards, the motherboard side
of the cable has to be terminated.)

> My opinion about IDE BUS is that it is not a suitable IO bus for mass
> storage devices, but looks like some extension of some system bus, since
it is.
> it is neither terminated, nor uses differential signals.
> If I enjoyed driving trabants with race car engine, I would probably
> use IDE Ultra 33 devices.

Gerard, you do need to realize that a 32bit CRC detects all single
byte, double byte, and triple byte errors. It detects (2^-32)-1 out of
2^32 of all quad byte and longer errors. Upto bursts of 64 bytes of
random data, this has a better chance of catching real errors than a
per-byte parity.

You're right that an unacceptable overhead would be incurred if
software would need to calculate the CRC. As to the speed of
calculating a CRC against that of parity, both can be implemented in
hardware with just a few xor gates.

Gerard, may I ask you a question on YOUR field of expertise? I got a
SCSI disk last thursday, and connected it to my '810 card. The disk
didn't have any labelled jumpers, but as it had been at the end of the
chain, I gathered that it must have been terminated. So I Assumed that
this was the case, and hooked it up like that. It turned out that I
was wrong, and the disk was unterminated.

With this as the hardware situtation, my machine once locked. I would
expect SERIOUS failures when my system would be using SCSI as the
root-device, but as it is, just a few "large" storage partitions were
mounted on the SCSI disks. With bad termination, I'd expect parity
errors, timeouts, but not a complete lockup.


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