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SubjectRe: [sx]quake still segfaults with 2.0.32 and MMX pentium

On Thu, 27 Nov 1997, Adam Wiggins wrote:

> > hm, is there any official INVLPG errata in MMX pentiums? Also, this might
> > be similar to the 4MB pages + overclocking problem, does anyone see this
> > bug with non-overclocked, never-ever-crashed MMX pentiums?
>
> I have a pent mmx 200 that got this problem. I also know a few ppl
> with 200's and 166's mmx's that had this problem. Thing is why does 2.1.X
> kernels fix it. Other that this *minor* bug the machine works fine and
> only sometimes locks up when switching for VC's to svgalib programs or
> VC's to X and visa versa.

thanks. It might or might not be a minor bug. _if_ it's a CPU bug and if
the 'erroneous' TLB is just invalid ... then this is a minor issue. (no
security risk, 'only' application stability risk). If it's the previous
TLB, or a random TLB, then that page might point to anything, /etc/shadow
contents or whatever other info.

if it's a kernel bug (eg. we forgot to invalidate something), then it's
highly unlikely that only Quake would encounter it. Quake really runs
pentiums at their full speed.

to test the CPU-bug theory, i've changed invlpg() to issue _two_ INVLPG
machine instructions. If this patch fixes the segfault problem, then we
are one step closer to say it's a CPU bug? [changing invlpg() to be a full
invalidation has 'bigger' impact on TLB management than two INVLPG's, and
also it might silently fix kernel bugs]

the attached diagnostic patch is against 2.0.3x kernels. I'm _really_
curious wether it changes the behavior :)

-- mingo

--- linux/include/asm-i386/.pgtable.h Thu Nov 27 14:23:25 1997
+++ linux/include/asm-i386/pgtable.h Thu Nov 27 14:23:56 1997
@@ -46,7 +46,7 @@
#define __flush_tlb_one(addr) flush_tlb()
#else
#define __flush_tlb_one(addr) \
-__asm__ __volatile__("invlpg %0": :"m" (*(char *) addr))
+__asm__ __volatile__("invlpg %0; invlpg %0;": :"m" (*(char *) addr))
#endif

#ifndef __SMP__

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