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SubjectRe: queuing & scheduling hints needed
On Wed, 22 Jan 1997, Natalia Kruszynska-Straszewicz wrote:

> Linux kernel I have:
> 2.0.x - I can upgrade if needed
> device:
> PCI bus to VME bus adaptor of bit3 ( model 617 ) for physics
> problem:
> writing driver for the device with mmap & DMA together, when DMA
> demands cease of all the other activities on the device ( on the
> bus-to-bus cable ) incl interrupts.
> my experience:
> SunOs drivers for different SPARCS ,also for VME adaptors on SPARC.
> Slow control & data acquisition for physics
> Linux Kernel Beginner
> my question:
> asking good hints in queuing & scheduling & process control
> ------------------------------------------------------------
> Dear Linux Gurus,
> I have a device which is nice to write a driver to, except
> for one thing. The device has it's own DMA engine.For the
> duration of it's DMA all the other activity have to cease.
> On the other side, the device allows to build VME bus access
> on PC, using mmap for slow control access ( several addresses)
> and read/write DMA access over several base VME spaces with
> lseek to set the DMA address.
> I can get the table of my user-processes collected them from the
> open/mmap calls in my driver. My question is how to put them to
> a short nap during my DMA in the most linux-like elegant way.
> After a bit more reading of kernel I can hack my way with
> the ax through tq_xxx queues of the sched.c, may be copying
> a bit of code. May be I will learn on time how to (un)mark them
> as awaiting I/O. I would like the kernel to do most of the job.
> Certainly you can give me a hint how to achieve my goal by
> something elegant & quick. I would also welcome recommendation
> of a good book concerning kernel services. I am using the kernel
> code and Linux Kernel Hacker's guide if Michael K.Johnson
> obtained from the net (+ several articles found also there).
> It's good, but I miss the index.
> Sincere greetings from your Linux Kernel Beginner
> Nata
You should NOT have to. The nature of DMA forces all other bus activity
to cease. That's why DMA is only allowed in "bursts" of a few words at
a time. The PC/AT DMA controller (which you will not be using) uses
the DRQ# and DAK# lines to synchronize. An external controller will
use I/O CH RDY to do the same thing. This line should not be pulled
low (not READY) for more than 2.5 microseconds. At 140ns per word
transfer, you can send 2500 / 140 = 17 words per burst.

Dick Johnson
Richard B. Johnson
Project Engineer
Analogic Corporation
Voice : (508) 977-3000 ext. 3754
Fax : (508) 532-6097
Modem : (508) 977-6870
Ftp :
Email :,
Penguin : Linux version 2.1.21 on an i586 machine (66.15 BogoMips).
Warning : It's hard to remain at the trailing edge of technology.

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